Patent Inventor: Volker Hecht
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Inverting flip-flop for use in field programmable gate arrays
Inventor: Hecht, et al. | Patent Number: 7932745
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Circuits and methods for testing FPGA routing switches
Inventor: Greene, et al. | Patent Number: 7919977
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PLD providing soft wakeup logic
Inventor: Greene, et al. | Patent Number: 7884640
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Inverting flip-flop for use in field programmable gate arrays
Inventor: Hecht, et al. | Patent Number: 7816946
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Circuits and methods for testing FPGA routing switches
Inventor: Greene, et al. | Patent Number: 7804321
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Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage
Inventor: Hecht, et al. | Patent Number: 7593268
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Non-volatile memory with source-side column select
Inventor: Wang, et al. | Patent Number: 7522453
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Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop
Inventor: Reynolds, et al. | Patent Number: 7477071
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Field programmable gate array long line routing network
Inventor: Hecht | Patent Number: 7394286
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Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop
Inventor: Reynolds, et al. | Patent Number: 7365567
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Field programmable gate array long line routing network
Inventor: Hecht | Patent Number: 7212030
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Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage
Inventor: Hecht, et al. | Patent Number: 7161841
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Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop
Inventor: Reynolds, et al. | Patent Number: 7106100
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Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop
Inventor: Reynolds, et al. | Patent Number: 6777977
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Method of reducing test time for NVM cell-based FPGA
Inventor: Hecht, et al. | Patent Number: 6272655
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Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor
Inventor: Peng, et al. | Patent Number: 6137728
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Method for erasing nonvolatile memory cells in a field programmable gate array
Inventor: Hecht | Patent Number: 6125059
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Nonvolatile reprogrammable interconnect cell with programmable buried bitline
Inventor: Peng, et al. | Patent Number: 6072720