Patent Inventor: Toshiharu Saitoh

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LSSD-compatible edge-triggered shift register latch
Inventor: Ashton, et al. | Patent Number: 7543203

Method for testing embedded DRAM arrays
Inventor: Chadwick, et al. | Patent Number: 7237165

Testing and repair methodology for memories having redundancy
Inventor: Combs, et al. | Patent Number: 7222274

Method for testing embedded DRAM arrays
Inventor: Chadwick, et al. | Patent Number: 7073100

Self-timed and self-tested fuse blow
Inventor: Saitoh | Patent Number: 6819160

Reduced-pin integrated circuit I/O test
Inventor: Saitoh | Patent Number: 6397361

Low power LSSD flip flops and a flushable single clock splitter for flip flops
Inventor: Gregor, et al. | Patent Number: 6304122

Method and apparatus for testing the data output system of a memory system
Inventor: Saitoh | Patent Number: 5826006

Method and apparatus for testing the address system of a memory system
Inventor: Saitoh | Patent Number: 5689514

Piezoelectric type acceleration sensor with metallic case and resin package
Inventor: Matsumoto, et al. | Patent Number: 5679897

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