Patent Inventor: Rebecca L. Stamm
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Temporary halting of thread execution until monitoring of armed events to memory location identified in working registers
Inventor: Emer, et al. | Patent Number: 6675192
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Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit
Inventor: Emer, et al. | Patent Number: 6493741
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Conversion of internal processor register commands to I/O space addresses
Inventor: Stamm, et al. | Patent Number: 5481689
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Method and apparatus for ordering read and write operations using conflict bits in a write queue
Inventor: Stamm | Patent Number: 5432918
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Pipeline utilizing an integral cache for transferring data to and from a register
Inventor: Witek, et al. | Patent Number: 5430888
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Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills
Inventor: Stamm, et al. | Patent Number: 5404483
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Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills
Inventor: Stamm, et al. | Patent Number: 5404482
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Ensuring write ordering under writeback cache error conditions
Inventor: Stamm, et al. | Patent Number: 5347648
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Processor system with writeback cache using writeback and non writeback transactions stored in separate queues
Inventor: Stamm, et al. | Patent Number: 5317720
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Error transition mode for multi-processor system
Inventor: Stamm, et al. | Patent Number: 5155843
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Pipeline having an integral cache which processes cache misses and loads data in parallel
Inventor: Witek, et al. | Patent Number: 5148536
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Method and apparatus for filtering invalidate requests
Inventor: Durdan, et al. | Patent Number: 5058006