Patent Inventor: Raymond B. Essick IV
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Method and apparatus for nested instruction looping using implicit predicates
Inventor: Essick, IV, et al. | Patent Number: 7945768
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Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters
Inventor: May, et al. | Patent Number: 7415601
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Data processing system using multiple addressing modes for SIMD operations and method thereof
Inventor: Moyer, et al. | Patent Number: 7275148
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Queuing cache for vectors with elements in predictable order
Inventor: Moat, et al. | Patent Number: 7246203
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Bus filter for memory address translation
Inventor: Essick, IV, et al. | Patent Number: 7219209
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Streaming vector processor with reconfigurable interconnection switch
Inventor: Lucas, et al. | Patent Number: 7159099
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Scheduler of program instructions for streaming vector processor having interconnected functional units
Inventor: May, et al. | Patent Number: 7140019
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Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values
Inventor: Norris, et al. | Patent Number: 7100019
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Method of programming linear graphs for streaming vector computation
Inventor: May, et al. | Patent Number: 6934938
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Interconnection device with integrated storage
Inventor: May, et al. | Patent Number: 6850536
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Memory interface with fractional addressing
Inventor: May, et al. | Patent Number: 6799261