Patent Inventor: Nicholas D. Wade
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Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory
Inventor: Langendorf, et al. | Patent Number: 6725349
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Passive message ordering on a decentralized ring
Inventor: Neiger, et al. | Patent Number: 6574219
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Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics
Inventor: Langendorf, et al. | Patent Number: 6505282
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Least recently used replacement method with protection
Inventor: Wilkerson, et al. | Patent Number: 6393525
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Out-of-order snooping for multiprocessor computer systems
Inventor: Neiger, et al. | Patent Number: 6112283
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Method and apparatus for sharing a signal line between agents
Inventor: MacWilliams, et al. | Patent Number: 6112016
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Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface
Inventor: Wade | Patent Number: 5828854
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Method and apparartus for sharing a signal line between agents
Inventor: MacWilliams, et al. | Patent Number: 5822767
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Method and apparatus for arbitrating access requests to a shared computer system memory by a graphics controller and memory controller
Inventor: Wade | Patent Number: 5818464
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Deadlock avoidance mechanism and method for multiple bus topology
Inventor: Rabe, et al. | Patent Number: 5717873
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Scalable cache attributes for an input/output bus
Inventor: MacWilliams, et al. | Patent Number: 5651137
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Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge
Inventor: Solomon, et al. | Patent Number: 5625779
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Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface
Inventor: Wade | Patent Number: 5606672
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Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills
Inventor: Stamm, et al. | Patent Number: 5404483
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Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills
Inventor: Stamm, et al. | Patent Number: 5404482
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Ensuring write ordering under writeback cache error conditions
Inventor: Stamm, et al. | Patent Number: 5347648