Patent Inventor: Marc Tremblay

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Method and apparatus for synchronizing threads on a processor that supports transactional memory
Inventor: Chaudhry, et al. | Patent Number: 7930695

Selectively monitoring loads to support transactional program execution
Inventor: Tremblay, et al. | Patent Number: 7904664

Clotheslines
Inventor: Lewis, et al. | Patent Number: 7878342

Return address stack recovery in a speculative execution computing apparatus
Inventor: Chaudhry, et al. | Patent Number: 7836290

Continuing execution in scout mode while a main thread resumes normal execution
Inventor: Tremblay, et al. | Patent Number: 7836281

Cooperative preemption mechanism for garbage-collected multi-threaded computation
Inventor: Bush, et al. | Patent Number: 7831961

Selectively monitoring stores to support transactional program execution
Inventor: Tremblay, et al. | Patent Number: 7818510

Method and structure for explicit software control using scoreboard status information
Inventor: Tremblay, et al. | Patent Number: 7711928

Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor
Inventor: Caprioli, et al. | Patent Number: 7689813

System, method and data structure for simulated interaction with graphical objects
Inventor: Carmel, et al. | Patent Number: 7676356

Recovering a subordinate strand from a branch misprediction using state information from a primary strand
Inventor: Tremblay, et al. | Patent Number: 7664942

Effective elimination of delay slot handling from a front section of a processor pipeline
Inventor: Chaudhry, et al. | Patent Number: 7634644

Method and apparatus for using multiple threads to spectulatively execute instructions
Inventor: Chaudhry, et al. | Patent Number: 7634641

Preventing register data flow hazards in an SST processor
Inventor: Chaudhry, et al. | Patent Number: 7610470

Method and apparatus for parallel arithmetic operations
Inventor: Sudharsanan, et al. | Patent Number: 7587582

Multiple-thread processor with in-pipeline, thread selectable storage
Inventor: Joy, et al. | Patent Number: 7587581

Method and apparatus for supporting different modes of multi-threaded speculative execution
Inventor: Chaudhry, et al. | Patent Number: 7584346

Time-multiplexed speculative multi-threading to support single-threaded applications
Inventor: Chaudhry, et al. | Patent Number: 7574588

Generation of multiple checkpoints in a processor that supports speculative execution
Inventor: Chaudhry, et al. | Patent Number: 7571304

Working register file entries with instruction based lifetime
Inventor: Chaudhry, et al. | Patent Number: 7565511

Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level
Inventor: Chaudhry, et al. | Patent Number: 7523266

Enforcing memory-reference ordering requirements at the L2 cache level
Inventor: Chaudhry, et al. | Patent Number: 7519775

Patchable and/or programmable pre-decode
Inventor: Chaudhry, et al. | Patent Number: 7509481

Start transactional execution (STE) instruction to support transactional program execution
Inventor: Tremblay, et al. | Patent Number: 7500086

Storing results of resolvable branches during speculative execution to predict branches during non-speculative execution
Inventor: Tremblay, et al. | Patent Number: 7490229

Processor with register dirty bit tracking for efficient context switch
Inventor: Tremblay, et al. | Patent Number: 7490228

Entering scout-mode when stores encountered during execute-ahead mode exceed the capacity of the store buffer
Inventor: Chaudhry, et al. | Patent Number: 7484080

Method and apparatus for facilitating a fast restart after speculative execution
Inventor: Chaudhry, et al. | Patent Number: 7469334

Local and global register partitioning technique
Inventor: Tremblay, et al. | Patent Number: 7437534

Pipelined processor with multi-cycle grouping for instruction dispatch with inter-group and intra-group dependency checking
Inventor: Tremblay | Patent Number: 7430653

Fail instruction to support transactional program execution
Inventor: Tremblay, et al. | Patent Number: 7418577

Avoiding locks by transactionally executing critical sections
Inventor: Moir, et al. | Patent Number: 7398355

Selectively unmarking load-marked cache lines during transactional program execution
Inventor: Tremblay, et al. | Patent Number: 7389383

Facilitating value prediction to support speculative program execution
Inventor: Chaudhry, et al. | Patent Number: 7366880

Explicit store-to-instruction-space instruction for self-modifying code and ensuring memory coherence between instruction cache and shared memory using a no-snoop protocol
Inventor: Tremblay | Patent Number: 7360028

Patchable and/or programmable decode using predecode selection
Inventor: Chaudhry, et al. | Patent Number: 7353363

Switching method in a multi-threaded processor
Inventor: Joy, et al. | Patent Number: 7316021

Deferring loads and stores when a load buffer or store buffer fills during execute-ahead mode
Inventor: Chaudhry, et al. | Patent Number: 7293161

Mechanism for eliminating the restart penalty when reissuing deferred instructions
Inventor: Chaudhry, et al. | Patent Number: 7293160

Selectively performing fetches for store operations during speculative execution
Inventor: Chaudhry, et al. | Patent Number: 7277989

Method for reducing lock manipulation overhead during access to critical code sections
Inventor: Tremblay, et al. | Patent Number: 7269717

Selectively monitoring loads to support transactional program execution
Inventor: Tremblay, et al. | Patent Number: 7269694

Selectively monitoring stores to support transactional program execution
Inventor: Tremblay, et al. | Patent Number: 7269693

Method and apparatus for avoiding read-after-write hazards in an execute-ahead processor
Inventor: Chaudhry, et al. | Patent Number: 7263603

Avoiding register RAW hazards when returning from speculative execution
Inventor: Chaudhry, et al. | Patent Number: 7257700

Selective execution of deferred instructions in a processor that supports speculative execution
Inventor: Chaudhry, et al. | Patent Number: 7257699

Method and apparatus for avoiding write-after-read hazards in an execute-ahead processor
Inventor: Chaudhry, et al. | Patent Number: 7216219

Method and apparatus for supporting one or more servers on a single semiconductor chip
Inventor: Chaudhry, et al. | Patent Number: 7216202

Method and apparatus for releasing memory locations during transactional execution
Inventor: Moir, et al. | Patent Number: 7206903

Multiple-thread processor with in-pipeline, thread selectable storage
Inventor: Joy, et al. | Patent Number: 7185185

Facilitating efficient join operations between a head thread and a speculative thread
Inventor: Chaudhry, et al. | Patent Number: 7168076

Hardware message buffer for supporting inter-processor communication
Inventor: Chaudhry, et al. | Patent Number: 7152232

Method and apparatus for fixing bit errors encountered during cache references without blocking
Inventor: Tremblay, et al. | Patent Number: 7127643

Method and apparatus for providing fault-tolerance for temporary results within a CPU
Inventor: Tremblay, et al. | Patent Number: 7124331

Implicitly derived register specifiers in a processor
Inventor: Tremblay, et al. | Patent Number: 7117342

Selectively deferring instructions issued in program order utilizing a checkpoint and multiple deferral scheme
Inventor: Chaudhry, et al. | Patent Number: 7114060

Local and global register partitioning in a VLIW processor
Inventor: Tremblay, et al. | Patent Number: 7114056

Selectively unmarking load-marked cache lines during transactional program execution
Inventor: Tremblay, et al. | Patent Number: 7089374

Graphics system with just-in-time decompression of compressed graphics data
Inventor: Deering, et al. | Patent Number: 7071935

Method and apparatus for providing error correction within a register file of a CPU
Inventor: Tremblay, et al. | Patent Number: 7058877

Facilitating value prediction to support speculative program execution
Inventor: Chaudhry, et al. | Patent Number: 7051192

System, method and data structure for simulated interaction with graphical objects
Inventor: Carmel, et al. | Patent Number: 7050955

Thread suspension system and method using trapping instructions
Inventor: Bush, et al. | Patent Number: 7013454

Efficient handling of a large register file for context switching and function calls and returns
Inventor: Tremblay, et al. | Patent Number: 7010674

Efficient implementation of multiprecision arithmetic
Inventor: Tremblay, et al. | Patent Number: 6988121

Method frame storage using multiple memory circuits
Inventor: O'Connor, et al. | Patent Number: 6961843

Method frame storage using multiple memory circuits
Inventor: O'Connor, et al. | Patent Number: 6950923

Method and apparatus for decoupling tag and data accesses in a cache memory
Inventor: Chaudhry, et al. | Patent Number: 6944724

Processor with multiple-thread, vertically-threaded pipeline
Inventor: Joy, et al. | Patent Number: 6938147

Method and apparatus for delaying interfering accesses from other threads during transactional program execution
Inventor: Jacobson, et al. | Patent Number: 6938130

Automatic prefetch of pointers
Inventor: Tremblay, et al. | Patent Number: 6934809

Providing fault-tolerance by comparing addresses and data from redundant processors running in lock-step
Inventor: Chaudhry, et al. | Patent Number: 6862693

Method and apparatus for avoiding locks by speculatively executing critical sections
Inventor: Tremblay, et al. | Patent Number: 6862664

Method and apparatus for updating an error-correcting code during a partial line store
Inventor: Chaudhry, et al. | Patent Number: 6848071

Multiple-thread processor with single-thread interface shared among threads
Inventor: Joy, et al. | Patent Number: 6801997

Method and apparatus for using an assist processor and value speculation to facilitate prefetching for a primary processor
Inventor: Chaudhry, et al. | Patent Number: 6772321

Decompression bit processing with a general purpose alignment tool
Inventor: Sudharsanan, et al. | Patent Number: 6757820

Method and apparatus for facilitating flow control during accesses to cache memory
Inventor: Chaudhry, et al. | Patent Number: 6754775

Supporting inter-process communication through a conditional trap instruction
Inventor: Chaudhry, et al. | Patent Number: 6732363

Locking of computer resources
Inventor: Joy, et al. | Patent Number: 6725308

Marking memory elements based upon usage of accessed information during speculative execution
Inventor: Chaudhry, et al. | Patent Number: 6721944

Using an L2 directory to facilitate speculative loads in a multiprocessor system
Inventor: Chaudhry, et al. | Patent Number: 6721855

Method and apparatus for facilitating speculative loads in a multiprocessor system
Inventor: Chaudhry, et al. | Patent Number: 6718839

Multiple-thread processor for threaded software applications
Inventor: Tremblay, et al. | Patent Number: 6718457

Method and apparatus for facilitating exception handling using a conditional trap instruction
Inventor: Chaudhry, et al. | Patent Number: 6704862

Method and apparatus for facilitating speculative stores in a multiprocessor system
Inventor: Chaudhry, et al. | Patent Number: 6704841

Arbitration protocol for a shared data cache
Inventor: Tremblay, et al. | Patent Number: 6704822

Method and apparatus for supporting multiple cache line invalidations per cycle
Inventor: Chaudhry, et al. | Patent Number: 6701417

Switching method in a multi-threaded processor
Inventor: Joy, et al. | Patent Number: 6694347

Monitor entry and exit for a speculative thread during space and time dimensional execution
Inventor: Chaudhry, et al. | Patent Number: 6684398

Reverse directory for facilitating accesses involving a lower-level cache
Inventor: Chaudhry, et al. | Patent Number: 6684297

Method and apparatus for using an assist processor to prefetch instructions for a primary processor
Inventor: Chaudhry, et al. | Patent Number: 6681318

Converting an arbitrary fixed point value to a floating point value
Inventor: Sudharsanan, et al. | Patent Number: 6671796

Parallel join operation to support space and time dimensional program execution
Inventor: Chaudhry, et al. | Patent Number: 6658451

Decompression of three-dimensional graphics data using mesh buffer references to reduce redundancy of processing
Inventor: Deering, et al. | Patent Number: 6628277

Efficient implementation of multiprecision arithmetic
Inventor: Tremblay, et al. | Patent Number: 6625634

Shared write buffer for use by multiple processor units
Inventor: Tremblay, et al. | Patent Number: 6622219

Clustered architecture in a VLIW processor
Inventor: Tremblay, et al. | Patent Number: 6615338

Methods and apparatus for combining a plurality of memory access transactions
Inventor: Tremblay, et al. | Patent Number: 6571319

Compressing and decompressing graphics data using gosub-type instructions and direct and indirect attribute settings
Inventor: Deering, et al. | Patent Number: 6559842

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