Patent Inventor: James M. Dodd

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Device and method for maximizing performance on a memory interface with a variable number of channels
Inventor: Dodd, et al. | Patent Number: 7523230

Buffered writes and memory page control
Inventor: Dodd | Patent Number: 7469316

Method and apparatus to improve multi-CPU system performance for accesses to memory
Inventor: Dodd, et al. | Patent Number: 7404047

Precharge suggestion
Inventor: Dodd | Patent Number: 7159066

Memory transaction ordering
Inventor: Dodd, et al. | Patent Number: 7120765

Adaptive page management
Inventor: Dodd | Patent Number: 7076617

Dual-port buffer-to-memory interface
Inventor: Halbert, et al. | Patent Number: 7024518

Method and apparatus for controlling power states in a memory device utilizing state information
Inventor: Dodd, et al. | Patent Number: 7000133

Memory bus termination with memory unit having termination control
Inventor: Dodd, et al. | Patent Number: 6981089

Mapping data masks in hardware by controller programming
Inventor: Riesenman, et al. | Patent Number: 6957307

Device and method for maximizing performance on a memory interface with a variable number of channels
Inventor: Dodd, et al. | Patent Number: 6952745

Obtaining data mask mapping information
Inventor: Riesenman, et al. | Patent Number: 6952367

Obtaining data mask mapping information
Inventor: Riesenman, et al. | Patent Number: 6925013

Address decode
Inventor: Dodd, et al. | Patent Number: 6888777

System and method for controlling data flow direction in a memory system
Inventor: Dodd, et al. | Patent Number: 6862653

Obtaining data mask mapping information
Inventor: Riesenman, et al. | Patent Number: 6801459

Memory system with burst length shorter than prefetch length
Inventor: Dodd, et al. | Patent Number: 6795899

Early power-down digital memory device and method
Inventor: Riesenman, et al. | Patent Number: 6781911

Method and apparatus for reducing the rate of commands being issued if the rate exceeds a threshold which is based upon a temperature curve
Inventor: Williams, et al. | Patent Number: 6772352

Device and method for maximizing performance on a memory interface with a variable number of channels
Inventor: Dodd, et al. | Patent Number: 6766385

Dual-port buffer-to-memory interface
Inventor: Halbert, et al. | Patent Number: 6742098

Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory
Inventor: Langendorf, et al. | Patent Number: 6725349

Memory buffer arrangement
Inventor: Khandekar, et al. | Patent Number: 6639820

System and method for controlling power states of a memory device via detection of a chip select signal
Inventor: Dodd, et al. | Patent Number: 6618791

System and method for providing concurrent row and column commands
Inventor: Dodd, et al. | Patent Number: 6553449

Method and apparatus for automatically detecting whether a board level cache is implemented with Mcache
Inventor: Dodd, et al. | Patent Number: 6535956

System and method for providing reliable transmission in a buffered memory system
Inventor: Dodd, et al. | Patent Number: 6530006

Weighted throttling mechanism with rank based throttling for a memory system
Inventor: Williams, et al. | Patent Number: 6507530

Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics
Inventor: Langendorf, et al. | Patent Number: 6505282

Multi-tier point-to-point buffered memory interface
Inventor: Halbert, et al. | Patent Number: 6493250

Memory interface having source-synchronous command/address signaling
Inventor: Dodd, et al. | Patent Number: 6449213

System resource arbitration mechanism for a host bridge
Inventor: Hayek, et al. | Patent Number: 6442632

System resource arbitration mechanism for a host bridge
Inventor: Hayek, et al. | Patent Number: 6212589

Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
Inventor: Dodd, et al. | Patent Number: 6148380

Method and apparatus for automatically detecting a selected cache type
Inventor: Dodd, et al. | Patent Number: 5898856

Mechanism for enabling multi-bit counter values to reliably cross between clocking domains
Inventor: Dodd, et al. | Patent Number: 5894567

Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme
Inventor: Langendorf, et al. | Patent Number: 5640519

Performing speculative system memory reads prior to decoding device code
Inventor: Dodd, et al. | Patent Number: 5603010

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