Patent Examiner: Tat; Binh

«1

Method and arrangement providing for implementation granularity using implementation sets
Inventor: Kong, et al. | Patent Number: 8141010

Method of logic circuit synthesis and design using a dynamic circuit library
Inventor: Dhong, et al. | Patent Number: 8136061

Indeterminate state logic insertion
Inventor: Gerowitz, et al. | Patent Number: 8136059

Design structure including failing address register and compare logic for multi-pass repair of memory arrays
Inventor: Barth, Jr., et al. | Patent Number: 8132131

Analog circuit testing and test pattern generation
Inventor: Zjajo, et al. | Patent Number: 8122423

Generating models for integrated circuits with sensitivity-based minimum change to existing models
Inventor: Sheu, et al. | Patent Number: 8122406

Conversion of circuit description to an abstract model of the circuit
Inventor: Veller, et al. | Patent Number: 8122398

Self-propelling decoupling capacitor design for flexible area decoupling capacitor fill design flow
Inventor: Li | Patent Number: 8117581

LSSD compatibility for GSD unified global clock buffers
Inventor: Warnock, et al. | Patent Number: 8117579

System and method for on-chip-variation analysis
Inventor: Lu, et al. | Patent Number: 8117575

Method and system for point-to-point fast delay estimation for VLSI circuits
Inventor: Sze, et al. | Patent Number: 8108818

Method of routing a design to increase the quality of the design
Inventor: Sundararajan, et al. | Patent Number: 8104011

Semiconductor integrated circuit design supporting method, semiconductor integrated circuit design supporting system, and computer readable medium
Inventor: Imada | Patent Number: 8104010

Methods and apparatus for providing flexible timing-driven routing trees
Inventor: Hentschke, et al. | Patent Number: 8095904

Method and apparatus for modeling an integrated circuit in a computer aided design system
Inventor: McHugh | Patent Number: 8065648

Semiconductor device
Inventor: Kotani | Patent Number: 8065637

Method for efficiently checkpointing and restarting static timing analysis of an integrated circuit chip
Inventor: Kalafala, et al. | Patent Number: 8056038

Methods for manufacturing an electronic device using an electronically determined test member
Inventor: Saunders, et al. | Patent Number: 8056031

Power mesh for multiple frequency operation of semiconductor products
Inventor: Vogel, et al. | Patent Number: 8042072

Method and system for post-routing lithography-hotspot correction of a layout
Inventor: Tong, et al. | Patent Number: 8037428

Circuit clustering during placement
Inventor: Singh | Patent Number: 8006215

Method of calculating predictive shape of wire structure, calculation apparatus, and computer-readable recording medium
Inventor: Sawai, et al. | Patent Number: 7418677

Local preferred direction routing
Inventor: Malhotra, et al. | Patent Number: 7412682

Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout
Inventor: Fredrickson, et al. | Patent Number: 7398505

Clustering circuit paths in electronic circuit design
Inventor: Lin, et al. | Patent Number: 7392494

Method for auto enlarging bend portion width and computer readable recording medium for storing program thereof
Inventor: Kang | Patent Number: 7389483

Method for manufacturing an electronic device having an electronically determined physical test member
Inventor: Saunders, et al. | Patent Number: 7386816

Method and apparatus for optimizing thermal management system performance using full-chip thermal analysis of semiconductor chip designs
Inventor: Chandra | Patent Number: 7383520

Method and system for performing minimization of input count during structural netlist overapproximation
Inventor: Baumgartner, et al. | Patent Number: 7380222

Method and apparatus for integrated circuit datapath layout using a vector editor
Inventor: Rushing, et al. | Patent Number: 7376922

Method and computer program product for designing power distribution system in a circuit
Inventor: Douriet, et al. | Patent Number: 7376914

Method and timing harness for system level static timing analysis
Inventor: Ko | Patent Number: 7373626

Methods and mechanisms for extracting and reducing capacitor elements
Inventor: Lenahan | Patent Number: 7373620

Method and apparatus for facilitating cell placement for an integrated circuit design
Inventor: Farrahi, et al. | Patent Number: 7370305

System and method for designing and manufacturing LSI
Inventor: Watanuki | Patent Number: 7370304

Method of routing a design to increase the quality of the design
Inventor: Sundararajan, et al. | Patent Number: 7367007

Crosstalk error control apparatus, method, and program
Inventor: Katou | Patent Number: 7367004

Method of logic circuit synthesis and design using a dynamic circuit library
Inventor: Dhong, et al. | Patent Number: 7363609

Method and apparatus for scenario search based random generation of functional test suites
Inventor: Hamid | Patent Number: 7360184

Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver
Inventor: Baumgartner, et al. | Patent Number: 7356792

Exposure mask, optical proximity correction device, optical proximity correction method, manufacturing method of semiconductor device, and optical proximity correction program
Inventor: Akiyama | Patent Number: 7353493

Data processing in digital systems
Inventor: Goodnow, et al. | Patent Number: 7353486

Electronic design for integrated circuits based on process related variations
Inventor: White, et al. | Patent Number: 7353475

Method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance
Inventor: Chandra, et al. | Patent Number: 7353471

Method and apparatus for placement and routing cells on integrated circuit chips
Inventor: Ang, et al. | Patent Number: 7350173

Reporting of aspects and partitioning of automatically generated code according to a partitioning scheme
Inventor: Koh, et al. | Patent Number: 7350172

System and method for memory element characterization
Inventor: Agrawal, et al. | Patent Number: 7350170

Pattern forming method, mask manufacturing method, and LSI manufacturing method
Inventor: Abe | Patent Number: 7346882

Method of estimating wiring complexity degree in semiconductor integrated circuit
Inventor: Watanuki, et al. | Patent Number: 7346871

Conductor trace design to reduce common mode cross-talk and timing skew
Inventor: Brist, et al. | Patent Number: 7343576

Method of supporting wiring design, supporting apparatus using the method, and computer-readable recording medium
Inventor: Sawai | Patent Number: 7343574

Automatic tuning of signal timing
Inventor: Schumann | Patent Number: 7340707

Method and system for analyzing the quality of an OPC mask
Inventor: Golubtsov, et al. | Patent Number: 7340706

Method of supporting wiring design, supporting apparatus using the method, and computer-readable recording medium
Inventor: Sawai | Patent Number: 7337417

Semiconductor integrated circuit and method of designing the same
Inventor: Matsumura, et al. | Patent Number: 7334210

Method and apparatus to measure hardware cost of adding complex instruction extensions to a processor
Inventor: Sanghavi, et al. | Patent Number: 7334201

Method and computer program for spreading trace segments in an integrated circuit package design
Inventor: Guo | Patent Number: 7325216

Timing violation debugging inside place and route tool
Inventor: Dinter, et al. | Patent Number: 7325215

Nested design approach
Inventor: Bhatia, et al. | Patent Number: 7325213

Clock skew modelling using delay stamping
Inventor: Bistry | Patent Number: 7325211

Method and apparatus for computing feature density of a chip layout
Inventor: Rast, et al. | Patent Number: 7322018

Measure of analysis performed in property checking
Inventor: Levitt, et al. | Patent Number: 7318205

Method and device for automated layer generation for double-gate FinFET designs
Inventor: Aller, et al. | Patent Number: 7315994

Layout verification based on probability of printing fault
Inventor: Yang, et al. | Patent Number: 7313777

Register file and method for designing a register file
Inventor: Mochizuki | Patent Number: 7313768

$Method and apparatus for performing mapping onto field programmable gate arrays utilizing fracturable logic cells$

Method and apparatus for performing mapping onto field programmable gate arrays utilizing fracturable logic cells
Inventor: Yuan, et al. | Patent Number: 7308671

System and method for designing electrical trace lengths on printed circuit boards between impedance discontinuities
Inventor: Felton | Patent Number: 7308670

Method and apparatus for analyzing clock-delay, and computer product
Inventor: Homma | Patent Number: 7308665

Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routing
Inventor: Fung, et al. | Patent Number: 7308664

Data path synthesis apparatus and method for optimizing a behavioral design description being processed by a behavioral synthesis tool
Inventor: Jensen | Patent Number: 7305650

Method and system for context-specific mask writing
Inventor: Pack, et al. | Patent Number: 7302672

Interactive interface resource allocation in a behavioral synthesis tool
Inventor: Bowyer, et al. | Patent Number: 7302670

Method and apparatus to generate a wiring harness layout
Inventor: Pannala, et al. | Patent Number: 7296253

Method and apparatus for performing post-placement functional decomposition for field programmable gate arrays
Inventor: Singh, et al. | Patent Number: 7290239

Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability
Inventor: Fung, et al. | Patent Number: 7290232

Circuit verification using multiple engines
Inventor: Jain, et al. | Patent Number: 7281225

System-level test architecture for delivery of compressed tests
Inventor: Ravi, et al. | Patent Number: 7278123

Battery-optimized system-on-a-chip and applications thereof
Inventor: Henson, et al. | Patent Number: 7278119

Methods to gather and display pin congestion statistics using graphical user interface
Inventor: Gentry, et al. | Patent Number: 7275230

Design verification
Inventor: Bruce, et al. | Patent Number: 7269808

Correcting a mask pattern by selectively updating the positions of specific segments
Inventor: Aton | Patent Number: 7263684

Method and apparatus for initial state extraction
Inventor: Koelbl, et al. | Patent Number: 7260800

Cell library database and timing verification and withstand voltage verification systems for integrated circuit using the same
Inventor: Sakiyama, et al. | Patent Number: 7257801

Multiple buffer insertion in global routing
Inventor: Galatenko, et al. | Patent Number: 7257791

Technology migration for integrated circuits with radical design restrictions
Inventor: Allen, et al. | Patent Number: 7257783

Input/output cells with localized clock routing
Inventor: Garlepp | Patent Number: 7254797

Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability
Inventor: Fung, et al. | Patent Number: 7254789

Method and system for context-specific mask writing
Inventor: Pack, et al. | Patent Number: 7249342

Adaptable circuit blocks for use in multi-block chip design
Inventor: Cooke, et al. | Patent Number: 7249340

Technology mapping techniques for incomplete lookup tables
Inventor: Baeckler, et al. | Patent Number: 7249329

Density driven layout for RRAM configuration module
Inventor: Andreev, et al. | Patent Number: 7246337

Ramptime propagation on designs with cycles
Inventor: Zolotykh, et al. | Patent Number: 7246336

Routing with derivative frame awareness to minimize device programming time and test cost
Inventor: Trimberger, et al. | Patent Number: 7240320

Apparatus and method to facilitate hierarchical netlist checking
Inventor: Regnier | Patent Number: 7240316

Simulation method for semiconductor circuit device and simulator for semiconductor circuit device
Inventor: Usui | Patent Number: 7240308

High level synthesis method for semiconductor integrated circuit
Inventor: Ogawa, et al. | Patent Number: 7237220

Integrated circuit designing support apparatus and method for the same
Inventor: Kanamaru | Patent Number: 7234127

Method and system for context-specific mask inspection
Inventor: Pack, et al. | Patent Number: 7231628

Method, system and computer program product for automatically estimating pin locations and interconnect parasitics of a circuit layout
Inventor: Chan, et al. | Patent Number: 7228514

Circuit operation verification device and method
Inventor: Hosokawa | Patent Number: 7228513

«1