Patent Examiner: Saba; William G.

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Method of fabricating patterned epitaxial silicon films utilizing molecular beam epitaxy
Inventor: Bean, et al. | Patent Number: 5134090

Vertical transistor device fabricated with semiconductor regrowth
Inventor: Hollis, et al. | Patent Number: 5106778

Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth
Inventor: Fan, et al. | Patent Number: 5091333

Method for making solid state device utilizing ion implantation techniques
Inventor: Li | Patent Number: 5082793

Process for the production of semiconductor devices utilizing multi-step deposition and recrystallization of amorphous silicon
Inventor: Yamawaki, et al. | Patent Number: 5037774

Semiconductor embedded layer technology utilizing selective epitaxial growth methods
Inventor: Bozler, et al. | Patent Number: 5032538

Method for making solid-state device utilizing isolation grooves
Inventor: Li | Patent Number: 4946800

Single crystal films of cubic group II fluorides on semiconductor compounds
Inventor: Johnston, Jr., et al. | Patent Number: 4878956

Method of fabricating single crystal films of cubic group II fluorides on semiconductor componds by molecular beam epitaxy
Inventor: Johnston, Jr., et al. | Patent Number: 4870032

Semiconductor heterostructures having Ge.sub.x Si.sub.1-x layers on Si utilizing molecular beam epitaxy
Inventor: Bean, et al. | Patent Number: 4861393

Method of forming well regions for field effect transistors utilizing self-aligned techniques
Inventor: Yatsuda, et al. | Patent Number: 4851364

Method for buried channel field effect transistor for microwave and millimeter frequencies utilizing ion implantation
Inventor: | Patent Number: 4833095

Method for manufacturing a semiconductor device utilizing self-aligned contact regions
Inventor: Shibata | Patent Number: 4830971

Method for light-induced photolytic deposition simultaneously independently controlling at least two different frequency radiations during the process
Inventor: Krimmel, et al. | Patent Number: 4784963

Process for the manufacture of semiconductor layers on semiconductor bodies or for the diffusion of impurities from compounds into semiconductor bodies utilizing an additional generation of activated hydrogen
Inventor: Beneking | Patent Number: 4774195

Method of making bipolar semiconductor device with wall spacer
Inventor: Lane | Patent Number: 4746623

Method of producing sheets of crystalline material
Inventor: Bozler, et al. | Patent Number: 4727047

Method for fabricating buried channel field-effect transistor for microwave and millimeter frequencies
Inventor: Calviello | Patent Number: 4724220

High power MOSFET with low on-resistance and high breakdown voltage
Inventor: Lidow, et al. | Patent Number: 4705759

Method of depositing uniformly thick selective epitaxial silicon
Inventor: Corboy, Jr., et al. | Patent Number: 4698316

Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers
Inventor: Birrittella, et al. | Patent Number: 4663831

Method for prevention of autodoping of epitaxial layers
Inventor: Roth, et al. | Patent Number: 4662956

Process for improving the quality of epitaxial silicon films grown on insulating substrates utilizing oxygen ion conductor substrates
Inventor: Manasevit | Patent Number: 4661176

Growth of epitaxial films by plasma enchanced chemical vapor deposition (PE-CVD)
Inventor: Reif, et al. | Patent Number: 4659401

Fabrication of stacked MOS devices utilizing lateral seeding and a plurality of separate implants at different energies
Inventor: MacElwee, et al. | Patent Number: 4651408

Method of fabricating a junction field effect transistor utilizing epitaxial overgrowth and vertical junction formation
Inventor: Bencuya | Patent Number: 4651407

Semiconductor on insulator edge doping process using an expanded mask
Inventor: Leong | Patent Number: 4649626

Method of manufacturing a semiconductor device
Inventor: Foxon | Patent Number: 4640720

Semiconductor material on a substrate, said substrate comprising, in order, a layer of organic polymer, a layer of metal or metal alloy and a layer of dielectric material
Inventor: Hawkins | Patent Number: 4639277

Method of manufacturing semiconductor substrate
Inventor: Shimbo, et al. | Patent Number: 4638552

Selective area III-V growth and lift-off using tungsten patterning
Inventor: Derkits, Jr., et al. | Patent Number: 4637129

Epitaxially isolated semiconductor device process utilizing etch and refill technique
Inventor: Boland | Patent Number: 4636269

Chemical beam deposition method utilizing alkyl compounds in a carrier gas
Inventor: Tsang | Patent Number: 4636268

Method of fabricating titanium silicide gate electrodes and interconnections
Inventor: Lien, et al. | Patent Number: 4635347

Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth
Inventor: Fan, et al. | Patent Number: 4632712

Vapor phase epitaxial growth method of zinc selenide and zinc selenide-sulphide by organometallic chemical vapor deposition
Inventor: Fujita, et al. | Patent Number: 4632711

Vapor phase epitaxial growth of carbon doped layers of Group III-V materials
Inventor: Van Rees | Patent Number: 4632710

Method of fabricating defect free trench isolation devices
Inventor: Hunter, et al. | Patent Number: 4631803

Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon
Inventor: Zorinsky, et al. | Patent Number: 4628591

Method for manufacturing a semiconductor device utilizing self-aligned silicide regions
Inventor: Shibata | Patent Number: 4622735

Molecular beam epitaxial process
Inventor: Shih | Patent Number: 4622083

Method of forming isolation regions containing conductive patterns therein
Inventor: Kameyama, et al. | Patent Number: 4615104

Method of forming isolation regions containing conductive patterns therein
Inventor: Kameyama, et al. | Patent Number: 4615103

Method for growing low defect, high purity crystalline layers utilizing lateral overgrowth of a patterned mask
Inventor: Morrison, et al. | Patent Number: 4612072

Method of forming an indium phosphide-boron phosphide heterojunction bipolar transistor
Inventor: Pande | Patent Number: 4611388

Method for manufacturing and epitaxially isolated semiconductor utilizing etch and refill technique
Inventor: Boland | Patent Number: 4609413

Method for fabricating buried channel field effect transistor for microwave and millimeter frequencies utilizing molecular beam epitaxy
Inventor: Calviello | Patent Number: 4601096

Method of forming a metal film on a selectively diffused layer
Inventor: Moriya, et al. | Patent Number: 4597167

Process for manufacturing an integrated circuit with tantalum silicide connections utilizing self-aligned oxidation
Inventor: Baudrant, et al. | Patent Number: 4593454

Method for forming uniformly thick selective epitaxial silicon
Inventor: Corboy, Jr., et al. | Patent Number: 4592792

Method of fabricating a CCD read only memory utilizing dual-level junction formation
Inventor: Nash | Patent Number: 4592130

Method for manufacturing a semiconductor device utilizing self-aligned oxide-nitride masking
Inventor: Ouchi, et al. | Patent Number: 4591398

Metal organic chemical vapor deposition of 111-v compounds on silicon
Inventor: Vernon | Patent Number: 4588451

Process of manufacturing a high frequency bipolar transistor utilizing doped silicide with self-aligned masking
Inventor: Coello-Vera | Patent Number: 4586968

Method of manufacturing field-effect transistors utilizing self-aligned techniques
Inventor: Yatsuda, et al. | Patent Number: 4586238

Process for fabricating dielectrically isolated devices utilizing heating of the polycrystalline support layer to prevent substrate deformation
Inventor: Celler, et al. | Patent Number: 4581814

Growth of epitaxial films by chemical vapor deposition utilizing a surface cleaning step immediately before deposition
Inventor: Reif, et al. | Patent Number: 4579609

Process for forming retrograde dopant distributions utilizing simultaneous outdiffusion of dopants
Inventor: Mundt, et al. | Patent Number: 4578128

Method of making an improved group III-V semiconductor device utilizing a getter-smoothing layer
Inventor: Gossard, et al. | Patent Number: 4578127

Process for fabricating quantum-well devices utilizing etch and refill techniques
Inventor: Reed, et al. | Patent Number: 4575924

Method of forming self-aligned implanted channel-stop and buried layer utilizing non-single crystal alignment key
Inventor: Hulseweh | Patent Number: 4573257

Purging: a reliability assurance technique for semiconductor lasers utilizing a purging process
Inventor: Gordon, et al. | Patent Number: 4573255

Method for minimizing autodoping during epitaxial deposition utilizing a graded pattern subcollector
Inventor: Moksvold | Patent Number: 4571275

Method of producing isolated regions for an integrated circuit substrate
Inventor: Cogan | Patent Number: 4570330

Method of producing titanium nitride MOS device gate electrode
Inventor: Price, et al. | Patent Number: 4570328

Method of manufacturing a semiconductor device utilizing simultaneous diffusion from an ion implanted polysilicon layer
Inventor: Ishii, et al. | Patent Number: 4569123

Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing deposition of amorphous semiconductor layer
Inventor: Lim, et al. | Patent Number: 4569121

Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing ion implantation
Inventor: Stacy, et al. | Patent Number: 4569120

Metalorganic vapor phase epitaxial growth of group II-VI semiconductor materials
Inventor: Hoke, et al. | Patent Number: 4568397

Method for fabricating a dielectric isolated integrated circuit device
Inventor: Ishikawa, et al. | Patent Number: 4567646

Utilizing interdiffusion of sequentially deposited links of HgTe and CdTe
Inventor: Irvine, et al. | Patent Number: 4566918

Elimination of mask undercutting in the fabrication of InP/InGaAsP BH devices
Inventor: Nelson, et al. | Patent Number: 4566171

Method of producing single crystal film utilizing a two-step heat treatment
Inventor: Tamura, et al. | Patent Number: 4565584

Method for making semiconductor device utilizing molecular beam epitaxy to form the emitter layers
Inventor: Sakai, et al. | Patent Number: 4563807

Method of growth of compound semiconductor
Inventor: Akiyama, et al. | Patent Number: 4561916

Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions
Inventor: Slawinski, et al. | Patent Number: 4561172

Backside gettering of silicon wafers utilizing selectively annealed single crystal silicon portions disposed between and extending into polysilicon portions
Inventor: Hawkins | Patent Number: 4559086

Method of preparing single crystalline cubic silicon carbide layers
Inventor: Addamiano | Patent Number: 4556436

Furnace transient anneal process
Inventor: Collins, et al. | Patent Number: 4555273

CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well
Inventor: Hillenius, et al. | Patent Number: 4554726

Method of manufacturing a semiconductor device by means of a molecular beam technique
Inventor: Haisma, et al. | Patent Number: 4554030

Growth of lattice-graded epilayers
Inventor: Cook | Patent Number: 4548658

Method of manufacturing semiconductor device utilizing selective epitaxial growth under reduced pressure
Inventor: Hine | Patent Number: 4547231

I.sup.2 L Structure and fabrication process compatible with high voltage bipolar transistors
Inventor: Beasom | Patent Number: 4546539

Method of manufacturing semiconductor integrated circuit devices having dielectric isolation regions
Inventor: Suzuki | Patent Number: 4546538

Method for producing a semiconductor device utilizing V-groove etching and thermal oxidation
Inventor: Kawabe, et al. | Patent Number: 4546537

Method of making a gallium arsenide field effect transistor
Inventor: Reichert | Patent Number: 4545109

Transient capless annealing process for the activation of ion implanted compound semiconductors
Inventor: Clarke, et al. | Patent Number: 4544417

Method for forming aluminum oxide dielectric isolation in integrated circuits
Inventor: Poponiak, et al. | Patent Number: 4542579

Process for manufacturing a semi-conductor device of the type comprising at least one silicon layer deposited on an insulating substrate
Inventor: Croset, et al. | Patent Number: 4540452

Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking
Inventor: Pollack, et al. | Patent Number: 4538343

CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors
Inventor: Bohr, et al. | Patent Number: 4536947

Process of vapor phase epitaxy of compound semiconductors
Inventor: Ogura, et al. | Patent Number: 4533410

Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer
Inventor: Kinney, et al. | Patent Number: 4532700

Method for epitaxially growing Ge.sub.x Si.sub.1-x layers on Si utilizing molecular beam epitaxy
Inventor: Bean, et al. | Patent Number: 4529455

Method for the formation of buried gates of a semiconductor device utilizing etch and refill techniques
Inventor: Muraoka | Patent Number: 4528745

Method for forming a void free isolation structure utilizing etch and refill techniques
Inventor: Beyer, et al. | Patent Number: 4528047

Method for forming a void free isolation pattern utilizing etch and refill techniques
Inventor: Silvestri, et al. | Patent Number: 4526631

High temperature layered silicon structures
Inventor: Wilner, et al. | Patent Number: 4523964

CVD lateral epitaxial growth of silicon over insulators
Inventor: Bradbury, et al. | Patent Number: 4522662

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