Patent Class: Static Information Storage And Retrieval (365/189.08)

Description

This is the generic class for apparatus or corresponding processesfor the static storage and retrieval of information. For classificationherein, the storage system must be (1) static, (2) a singular storageelement or plural elements of the same type, (3) addressable. (1)Note. Static storage and retrieval of information withinthis class means that relative motion is not required between thestorage element and the source, receiver, or transducer. For dynamicstorage and retrieval or magnetic information, see References to OtherClasses, below. (2)Note. The storage elements within this class are plural elementsof the same type which may store one or more bits of informationper element. (3)Note. The storage system must be addressable, that is, theremust be an inherent means for writing information into a memoryand a means for reading the same information from the memory. Forswitching systems, selective systems, card readers, and recorders,see References to Other Classes, below. Static memory systems involvingdata processing techniques are classified elsewhere.

...7

Two side decoding of a memory array
Inventor: Kurihara, et al. | Patent Number: 6373742

Quad CAM cell with minimum cell size
Inventor: Lien, et al. | Patent Number: 6373739

Semiconductor memory for logic-hybrid memory
Inventor: Takase | Patent Number: 6370080

Random access memory
Inventor: Masgonty, et al. | Patent Number: 6366504

Arrangements of interface logic, memory core, data shift and pad blocks for integrated circuit memory devices
Inventor: Moon, et al. | Patent Number: 6362995

Semiconductor storage device
Inventor: Yoshimoto | Patent Number: 6356508

Efficient open-array memory device architecture and method
Inventor: Bissey, et al. | Patent Number: 6356474

PLD with on-chip memory having a shadow register
Inventor: Sample, et al. | Patent Number: 6353552

Static random access memory circuits
Inventor: Lee | Patent Number: 6353551

Synchronous semiconductor memory apparatus and input information latch control method thereof
Inventor: Higashiho, et al. | Patent Number: 6351432

Content-addressable memory implemented using programmable logic
Inventor: Guccione, et al. | Patent Number: 6351143

Buffering circuit embedded in an integrated circuit device module used for buffering clocks and other input signals
Inventor: Ochoa, et al. | Patent Number: 6347394

Prefetch and restore method and apparatus of semiconductor memory device
Inventor: Kim | Patent Number: 6345007

Semiconductor IC device having a memory and a logic circuit implemented with a single chip
Inventor: Watanabe, et al. | Patent Number: 6335898

Driving circuit of nonvolatile ferroelectric memory device and method for driving the same
Inventor: Kang | Patent Number: 6335877

Mixed signal method for display deflection signal generation for low cost displays
Inventor: Morrish | Patent Number: 6327193

Reading device and method for integrated circuit memory
Inventor: Fournel | Patent Number: 6324112

Parallel test for asynchronous memory
Inventor: Allan, et al. | Patent Number: 6324107

Pseudo-static leakage-tolerant register file bit-cell circuit
Inventor: Balamurugan, et al. | Patent Number: 6320795

Reduced impact from coupling noise in diagonal bitline architectures
Inventor: Mueller, et al. | Patent Number: 6320780

Semiconductor memory device equipped with serial/parallel conversion circuitry for testing memory cells
Inventor: Hayashi, et al. | Patent Number: 6317372

FPGA with on-chip multiport memory
Inventor: Sample, et al. | Patent Number: 6317367

Dynamic random access memory
Inventor: Okamura, et al. | Patent Number: 6317366

Static semiconductor memory device with expanded operating voltage range
Inventor: Nagaoka | Patent Number: 6316812

Semiconductor memory device with a plurality of memory blocks
Inventor: Ikeda | Patent Number: 6314045

Method and device for fast addressing redundant columns in a nonvolatile memory
Inventor: Condemi, et al. | Patent Number: 6310801

Circuits and method for multi-level data through a single input/output pin
Inventor: Derner | Patent Number: 6307800

Low power priority encoder
Inventor: Fuh | Patent Number: 6307767

Logic interface circuit and semiconductor memory device using this circuit
Inventor: Kim, et al. | Patent Number: 6304495

Read only memory integrated semiconductor device
Inventor: Schoellkopf | Patent Number: 6304480

Content addressable memory cell with a bootstrap improved compare
Inventor: Lachman, et al. | Patent Number: 6301140

Feedforward-controlled sense amplifier
Inventor: Nguyen | Patent Number: 6300816

Delay control circuit synchronous with clock signal
Inventor: Kamoshida, et al. | Patent Number: 6292411

Semiconductor memory
Inventor: Tokuda | Patent Number: 6292404

Programmable logic device memory array circuit having combinable single-port memory arrays
Inventor: Reddy, et al. | Patent Number: 6288970

Multi-port static random access memory design for column interleaved arrays
Inventor: Zhang, et al. | Patent Number: 6282143

Block RAM with reset to user selected value
Inventor: Pang, et al. | Patent Number: 6282127

Address decoder and method for ITS accelerated stress testing
Inventor: Hill, et al. | Patent Number: 6275442

Stability test for silicon on insulator SRAM memory cells utilizing disturb operations to stress memory cells under test
Inventor: Aipperspach, et al. | Patent Number: 6275427

Memory circuit including word line reset circuit and method of resetting word line
Inventor: Uehara | Patent Number: 6262934

Configuration bus interface circuit for FPGAS
Inventor: Schultz, et al. | Patent Number: 6262596

Cam array with minimum cell size
Inventor: Lien, et al. | Patent Number: 6256216

Large-capacity content addressable memory with sorted insertion
Inventor: Shectman | Patent Number: 6252790

Inter-row configurability of content addressable memory
Inventor: Pereira, et al. | Patent Number: 6252789

Semiconductor IC device having a memory and a logic circuit implemented with a single chip
Inventor: Watanabe, et al. | Patent Number: 6246629

Semiconductor memory equipped with row address decoder having reduced signal propagation delay time
Inventor: Yokozeki | Patent Number: 6243319

Sample and load scheme for observability internal nodes in a PLD
Inventor: Patel, et al. | Patent Number: 6243304

Low area impact technique for doubling the write data bandwidth of a memory array
Inventor: Barry, et al. | Patent Number: 6240038

Content addressable memory protection circuit and method
Inventor: Polizzi, et al. | Patent Number: 6240002

Content addressable memory with reduced transient current
Inventor: Sywyk, et al. | Patent Number: 6240000

Programmable logic device with multi-port memory
Inventor: Sample, et al. | Patent Number: 6219284

Memory device having line address counter for making next line active while current line is processed
Inventor: Anraku | Patent Number: 6215719

Static RAM having word line driving circuitry shared by all the memory cells provided therein
Inventor: Noda | Patent Number: 6212124

Translation lookaside buffer (TLB) including fast hit signal generation circuitry
Inventor: Tupuri, et al. | Patent Number: 6208543

Method and apparatus for measuring subthreshold current in a memory array
Inventor: Venkatesh, et al. | Patent Number: 6201747

Voltage phase generator with increased driving capacity
Inventor: Calafato, et al. | Patent Number: 6198672

Memory device having a controller capable of disabling data input/output mask (DQM) input buffer during portions of a read operation and a write operation
Inventor: Jeong, et al. | Patent Number: 6192429

Semiconductor memory device having decreased layout area and method of manufacturing the same
Inventor: Toda | Patent Number: 6192000

Programmable logic device memory array circuit having combinable single-port memory arrays
Inventor: Reddy, et al. | Patent Number: 6191998

Magnetic random access memory circuit
Inventor: Miura, et al. | Patent Number: 6191972

Selective match line discharging in a partitioned content addressable memory array
Inventor: Pereira | Patent Number: 6191969

Semiconductor memory having memory bank decoders disposed symmetrically on a chip
Inventor: Le | Patent Number: 6188634

Reduced-pitch 6-transistor NMOS content-addressable-memory cell
Inventor: Ong | Patent Number: 6188594

Method and apparatus for a flexible controller for a DRAM generator system
Inventor: Weinfurtner | Patent Number: 6181639

Integrated circuit memory having a sense amplifier activated based on word line potentials
Inventor: Le, et al. | Patent Number: 6181624

Boosted-voltage drive circuit operable with high reliability and semiconductor memory device employing the same
Inventor: Tomishima, et al. | Patent Number: 6178122

Method for controlling high speed digital electronic memory
Inventor: Jennings | Patent Number: 6169703

Data encoding for content addressable memories
Inventor: Wong | Patent Number: 6166938

Configuration for crosstalk attenuation in word lines of DRAM circuits
Inventor: Brox, et al. | Patent Number: 6160747

Semiconductor memory device having a delay circuit set according to the storage capacity of a memory macro
Inventor: Yabe, et al. | Patent Number: 6154396

Programmable logic device with multi-port memory
Inventor: Sample, et al. | Patent Number: 6151258

FPGA with embedded content-addressable memory
Inventor: Kawana, et al. | Patent Number: 6147890

Method and apparatus for an improved reset and power-on arrangement for DRAM generator controller
Inventor: Weinfurtner | Patent Number: 6141284

Method and apparatus for generating a signal with a voltage insensitive or controlled delay
Inventor: Mecier, et al. | Patent Number: 6141266

Programmable logic array integrated circuit incorporating a first-in first-out memory
Inventor: Lytle, et al. | Patent Number: 6134166

Programmable address decoder for field programmable memory array
Inventor: Gould, et al. | Patent Number: 6130854

Memory integrated circuit device including a memory having a configuration suitable for mixture with logic
Inventor: Ohtani, et al. | Patent Number: 6130852

Method of operating a field programmable memory array with a field programmable gate array
Inventor: Gould, et al. | Patent Number: 6118707

Electrically erasable non-volatile memory cell with integrated SRAM cell to reduce testing time
Inventor: Ma | Patent Number: 6118693

Method and apparatus for reading multiple matched addresses
Inventor: Martin | Patent Number: 6118682

Synchronous dynamic random access memory with four-bit data prefetch
Inventor: Koelling, et al. | Patent Number: 6115321

Separate byte control on fully synchronous pipelined SRAM
Inventor: Mick, et al. | Patent Number: 6115320

Parallel test for asynchronous memory
Inventor: Allan, et al. | Patent Number: 6111800

Write recovery time control circuit in semiconductor memory and control method thereof
Inventor: Rha | Patent Number: 6108245

Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times
Inventor: Manning | Patent Number: 6105106

Integrated circuit clock input buffer
Inventor: Merritt | Patent Number: 6104643

Block RAM with reset
Inventor: Goetting, et al. | Patent Number: 6101132

Semiconductor IC device having a memory and a logic circuit implemented with a single chip
Inventor: Watanabe, et al. | Patent Number: 6097663

Elementary storage circuits
Inventor: Ramanadin | Patent Number: 6091664

Data access device for DRAM
Inventor: Lee | Patent Number: 6091661

Semiconductor memory device having a plurality of banks activated by a common timing control circuit
Inventor: Takahashi | Patent Number: 6088292

Counter circuit and semiconductor memory having counter circuit as address counter circuit
Inventor: Shirai, et al. | Patent Number: 6078636

Pipelined dual port integrated circuit memory
Inventor: Roth, et al. | Patent Number: 6078527

Method and apparatus for a RAM circuit having N-nary word line generation
Inventor: Horne, et al. | Patent Number: 6069836

Internal clock multiplication for test time reduction
Inventor: Komai, et al. | Patent Number: 6069829

Word configuration programmable semiconductor memory with multiple word configuration programming mode
Inventor: Kozaru | Patent Number: 6067597

Static semiconductor memory device operating at high speed under lower power supply voltage
Inventor: Yamashita, et al. | Patent Number: 6067256

Semiconductor memory device and memory system
Inventor: Muranaka, et al. | Patent Number: 6064605

Methods and apparatus for reading memory device register data
Inventor: Manning | Patent Number: 6064600

Memory device with reduced power dissipation
Inventor: Baroni, et al. | Patent Number: 6061286

...7

Patent Class: Static Information Storage And Retrieval (365/189.08)

Two side decoding of a memory array

Quad CAM cell with minimum cell size

Semiconductor memory for logic-hybrid memory

Random access memory

Arrangements of interface logic, memory core, data shift and pad blocks for integrated circuit memory devices

Semiconductor storage device

Efficient open-array memory device architecture and method

PLD with on-chip memory having a shadow register

Static random access memory circuits

Synchronous semiconductor memory apparatus and input information latch control method thereof

Content-addressable memory implemented using programmable logic

Buffering circuit embedded in an integrated circuit device module used for buffering clocks and other input signals

Prefetch and restore method and apparatus of semiconductor memory device

Semiconductor IC device having a memory and a logic circuit implemented with a single chip

Driving circuit of nonvolatile ferroelectric memory device and method for driving the same

Mixed signal method for display deflection signal generation for low cost displays

Reading device and method for integrated circuit memory

Parallel test for asynchronous memory

Pseudo-static leakage-tolerant register file bit-cell circuit

Reduced impact from coupling noise in diagonal bitline architectures

Semiconductor memory device equipped with serial/parallel conversion circuitry for testing memory cells

FPGA with on-chip multiport memory

Dynamic random access memory

Static semiconductor memory device with expanded operating voltage range

Semiconductor memory device with a plurality of memory blocks

Method and device for fast addressing redundant columns in a nonvolatile memory

Circuits and method for multi-level data through a single input/output pin

Low power priority encoder

Logic interface circuit and semiconductor memory device using this circuit

Read only memory integrated semiconductor device

Content addressable memory cell with a bootstrap improved compare

Feedforward-controlled sense amplifier

Delay control circuit synchronous with clock signal

Semiconductor memory

Programmable logic device memory array circuit having combinable single-port memory arrays

Multi-port static random access memory design for column interleaved arrays

Block RAM with reset to user selected value

Address decoder and method for ITS accelerated stress testing

Stability test for silicon on insulator SRAM memory cells utilizing disturb operations to stress memory cells under test

Memory circuit including word line reset circuit and method of resetting word line

Configuration bus interface circuit for FPGAS

Cam array with minimum cell size

Large-capacity content addressable memory with sorted insertion

Inter-row configurability of content addressable memory

Semiconductor IC device having a memory and a logic circuit implemented with a single chip

Semiconductor memory equipped with row address decoder having reduced signal propagation delay time

Sample and load scheme for observability internal nodes in a PLD

Low area impact technique for doubling the write data bandwidth of a memory array

Content addressable memory protection circuit and method

Content addressable memory with reduced transient current

Programmable logic device with multi-port memory

Memory device having line address counter for making next line active while current line is processed

Static RAM having word line driving circuitry shared by all the memory cells provided therein

Translation lookaside buffer (TLB) including fast hit signal generation circuitry

Method and apparatus for measuring subthreshold current in a memory array

Voltage phase generator with increased driving capacity

Memory device having a controller capable of disabling data input/output mask (DQM) input buffer during portions of a read operation and a write operation

Semiconductor memory device having decreased layout area and method of manufacturing the same

Programmable logic device memory array circuit having combinable single-port memory arrays

Magnetic random access memory circuit

Selective match line discharging in a partitioned content addressable memory array

Semiconductor memory having memory bank decoders disposed symmetrically on a chip

Reduced-pitch 6-transistor NMOS content-addressable-memory cell

Method and apparatus for a flexible controller for a DRAM generator system

Integrated circuit memory having a sense amplifier activated based on word line potentials

Boosted-voltage drive circuit operable with high reliability and semiconductor memory device employing the same

Method for controlling high speed digital electronic memory

Data encoding for content addressable memories

Configuration for crosstalk attenuation in word lines of DRAM circuits

Semiconductor memory device having a delay circuit set according to the storage capacity of a memory macro

Programmable logic device with multi-port memory

FPGA with embedded content-addressable memory

Method and apparatus for an improved reset and power-on arrangement for DRAM generator controller

Method and apparatus for generating a signal with a voltage insensitive or controlled delay

Programmable logic array integrated circuit incorporating a first-in first-out memory

Programmable address decoder for field programmable memory array

Memory integrated circuit device including a memory having a configuration suitable for mixture with logic

Method of operating a field programmable memory array with a field programmable gate array

Electrically erasable non-volatile memory cell with integrated SRAM cell to reduce testing time