Patent Attorney: Taylor; John P.

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Process for locating, displaying, analyzing, and optionally monitoring potential transient defect sites in one or more integrated circuit chips of a semiconductor substrate
Inventor: DiBiase | Patent Number: 7202094

Process for removal of photoresist mask used for making vias in low K carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist mask
Inventor: Kim, et al. | Patent Number: 7071113

Process and apparatus for integrating sheet resistance measurements and reflectance measurements of a thin film in a common apparatus
Inventor: Johnson, et al. | Patent Number: 7050160

Low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation
Inventor: Aronowitz, et al. | Patent Number: 7015168

Process for locating, displaying, analyzing, and optionally monitoring potential transient defect sites in one or more integrated circuit chips of a semiconductor substrate
Inventor: DiBiase | Patent Number: 6977183

Carbon nanotube memory cell for integrated circuit structure with removable side spacers to permit access to memory cell and process for forming such memory cell
Inventor: Burke, et al. | Patent Number: 6955937

Apparatus comprising a flexible vacuum seal pad structure capable of retaining non-planar substrates thereto
Inventor: Boyd, et al. | Patent Number: 6942265

Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for integrated circuit structure
Inventor: Catabay, et al. | Patent Number: 6930056

Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material
Inventor: Aronowitz, et al. | Patent Number: 6858195

PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER
Inventor: Kwak, et al. | Patent Number: 6838379

Structure and method for mounting a small sample in an opening in a larger substrate
Inventor: Tortonese, et al. | Patent Number: 6821812

Alignment process for integrated circuit structures on semiconductor substrate using scatterometry measurements of latent images in spaced apart test fields on substrate
Inventor: Yates, et al. | Patent Number: 6809824

Fuse construction for integrated circuit structure having low dielectric constant dielectric material
Inventor: Liu, et al. | Patent Number: 6806551

Low k dielectric composite layer for integrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning
Inventor: Catabay, et al. | Patent Number: 6800940

Integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines
Inventor: Li, et al. | Patent Number: 6794756

Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for intergrated circuit structure
Inventor: Catabay, et al. | Patent Number: 6790784

Process for inhibiting edge peeling of coating on semiconductor substrate during formation of integrated circuit structure thereon
Inventor: Young, et al. | Patent Number: 6767692

Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrate
Inventor: Aronowitz, et al. | Patent Number: 6759337

Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same
Inventor: Catabay, et al. | Patent Number: 6756674

Process for reducing defects in copper-filled vias and/or trenches formed in porous low-k dielectric material
Inventor: Kim | Patent Number: 6723653

Apparatus and method for removably adhering a semiconductor substrate to a substrate support
Inventor: Lent | Patent Number: 6722026

Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures
Inventor: Nagahara, et al. | Patent Number: 6713394

PROCESS FOR REMOVAL OF PHOTORESIST MASK USED FOR MAKING VIAS IN LOW K CARBON-DOPED SILICON OXIDE DIELECTRIC MATERIAL, AND FOR REMOVAL OF ETCH RESIDUES FROM FORMATION OF VIAS AND REMOVAL OF PHOTORESIST MASK
Inventor: Kim, et al. | Patent Number: 6673721

Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation
Inventor: Aronowitz, et al. | Patent Number: 6649219

Process for forming integrated circuit structure comprising layer of low k dielectric material having antireflective properties in an upper surface
Inventor: Catabay, et al. | Patent Number: 6613665

Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate
Inventor: Pallinti, et al. | Patent Number: 6607967

Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure
Inventor: Allman, et al. | Patent Number: 6583026

Process for forming a low dielectric constant fluorine and carbon containing silicon oxide dielectric material
Inventor: Zubkov, et al. | Patent Number: 6572925

Process for improving mechanical strength of layers of low k dielectric material
Inventor: May, et al. | Patent Number: 6566244

Fuse construction for integrated circuit structure having low dielectric constant dielectric material
Inventor: Liu, et al. | Patent Number: 6566171

Control of reaction rate in formation of low k carbon-containing silicon oxide dielectric material using organosilane, unsubstituted silane, and hydrogen peroxide reactants
Inventor: Allman, et al. | Patent Number: 6562735

Process for removal of resist mask over low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and removal of residues from via etch and resist mask removal
Inventor: Gu, et al. | Patent Number: 6562700

Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning
Inventor: Kim, et al. | Patent Number: 6559048

Processing for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines
Inventor: Hu, et al. | Patent Number: 6559033

Process for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines
Inventor: Bhatt, et al. | Patent Number: 6537923

Process for treating porous low k dielectric material in damascene structure to form a non-porous dielectric diffusion barrier on etched via and trench surfaces in the porous low k dielectric material
Inventor: Catabay, et al. | Patent Number: 6537896

PROCESS FOR FORMING COMPOSITE OF BARRIER LAYERS OF DIELECTRIC MATERIAL TO INHIBIT MIGRATION OF COPPER FROM COPPER METAL INTERCONNECT OF INTEGRATED CIRCUIT STRUCTURE INTO ADJACENT LAYER OF LOW K DIELECTRIC MATERIAL
Inventor: Catabay, et al. | Patent Number: 6528423

FORMATION OF IMPROVED LOW DIELECTRIC CONSTANT CARBON-CONTAINING SILICON OXIDE DIELECTRIC MATERIAL BY REACTION OF CARBON-CONTAINING SILANE WITH OXIDIZING AGENT IN THE PRESENCE OF ONE OR MORE REACTION RETARDANTS
Inventor: Sukharev | Patent Number: 6524974

Process for forming high dielectric constant gate dielectric for integrated circuit structure
Inventor: Aronowitz, et al. | Patent Number: 6511925

Integrated circuit structures having low k porous aluminum oxide dielectric material separating aluminum lines, and method of making same
Inventor: Sukharev | Patent Number: 6506678

Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning
Inventor: Catabay, et al. | Patent Number: 6503840

Process for selective polishing of metal-filled trenches of integrated circuit structures
Inventor: Nagahara, et al. | Patent Number: 6503828

Composite low dielectric constant film for integrated circuit structure
Inventor: Catabay, et al. | Patent Number: 6492731

Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures
Inventor: Nagahara, et al. | Patent Number: 6489242

Reduced soft error rate (SER) construction for integrated circuit structures
Inventor: Liu, et al. | Patent Number: 6472715

Process for forming low K dielectric material between metal lines
Inventor: Catabay, et al. | Patent Number: 6423630

Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines
Inventor: Li, et al. | Patent Number: 6423628

Process for inhibiting crack formation in low dielectric constant dielectric films of integrated circuit structure
Inventor: Catabay, et al. | Patent Number: 6420277

Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing
Inventor: Xie, et al. | Patent Number: 6417093

Low k dielectric composite layer for intergrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning
Inventor: Catabay, et al. | Patent Number: 6391795

Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure
Inventor: Lee, et al. | Patent Number: 6391768

LOW TEMPERATURE PROCESS FOR FORMING A LOW DIELECTRIC CONSTANT FLUORINE AND CARBON-CONTAINING SILICON OXIDE DIELECTRIC-MATERIAL CHARACTERIZED BY IMPROVED RESISTANCE TO OXIDATION AND GOOD GAP-FILLING CAPABILITIES
Inventor: Sukharev, et al. | Patent Number: 6365528

Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers
Inventor: Aronowitz, et al. | Patent Number: 6331468

Process for forming shaped group III-V semiconductor nanocrystals, and product formed using process
Inventor: Alivisatos, et al. | Patent Number: 6306736

Sidewall structure for metal interconnect and method of making same
Inventor: Kapoor, et al. | Patent Number: 6303995

Low dielectric constant multiple carbon-containing silicon oxide dielectric material for use in integrated circuit structures, and method of making same
Inventor: Aronowitz, et al. | Patent Number: 6303047

Anodized aluminum susceptor for forming integrated circuit structures and method of making anodized aluminum susceptor
Inventor: Telford, et al. | Patent Number: 6242111

Integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level, and process for making same
Inventor: Pasch, et al. | Patent Number: 6239491

Process to prevent stress cracking of dielectric films on semiconductor wafers
Inventor: Catabay, et al. | Patent Number: 6232658

Process for forming shaped group II-VI semiconductor nanocrystals, and product formed using process
Inventor: Alivisatos, et al. | Patent Number: 6225198

Method for rotationally aligning and degassing semiconductor substrate within single vacuum chamber
Inventor: Davenport | Patent Number: 6222991

Inductor with cobalt/nickel core for integrated circuit structure with high inductance and high Q-factor
Inventor: Qian, et al. | Patent Number: 6166422

Laser marking of semiconductor wafer substrate while inhibiting adherence to substrate surface of particles generated during laser marking
Inventor: Sato, et al. | Patent Number: 6156676

Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same
Inventor: Puchner, et al. | Patent Number: 6156620

Modified multilayered metal line structure for use with tungsten-filled vias in integrated circuit structures
Inventor: Hsia, et al. | Patent Number: 6147409

Well formation For CMOS devices integrated circuit structures
Inventor: Puchner, et al. | Patent Number: 6144076

Apparatus and process for deposition of thin film on semiconductor substrate while inhibiting particle formation and deposition
Inventor: Zhang, et al. | Patent Number: 6127286

Multiple step ionized metal plasma deposition process for conformal step coverage
Inventor: Liu, et al. | Patent Number: 6080285

Process for forming re-entrant geometry for gate electrode of integrated circuit structure
Inventor: Owyang, et al. | Patent Number: 6060375

Process for abrasive removal of copper from the back surface of a silicon substrate
Inventor: Pasch, et al. | Patent Number: 6059637

Process for forming vias, and trenches for metal lines, in multiple dielectric layers of integrated circuit structure
Inventor: Hsia, et al. | Patent Number: 6037262

Process for forming metal silicide contacts using amorphization of exposed silicon while minimizing device degradation
Inventor: Tsai, et al. | Patent Number: 6010952

Metal-filled via/contact opening with thin barrier layers in integrated circuit structure for fast response, and process for making same
Inventor: Zhao, et al. | Patent Number: 5994775

Process for forming self-aligned conductive plugs in multiple insulation levels in integrated circuit structures and resulting product
Inventor: Kapoor | Patent Number: 5985746

Apparatus and method for rotationally aligning and degassing semiconductor substrate within single vacuum chamber
Inventor: Davenport | Patent Number: 5982986

Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step
Inventor: Liu, et al. | Patent Number: 5953614

Etch process selective to cobalt silicide for formation of integrated circuit structures
Inventor: Yoshikawa, et al. | Patent Number: 5933757

Process for low energy implantation of semiconductor substrate using channeling to form retrograde wells
Inventor: Aronowitz, et al. | Patent Number: 5904551

Process for forming photoresist mask over integrated circuit structures with critical dimension control
Inventor: Schoenborn, et al. | Patent Number: 5902704

Process for forming improved cobalt silicide layer on integrated circuit structure using two capping layers
Inventor: Yoshikawa, et al. | Patent Number: 5902129

Formation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantation
Inventor: Aronowitz, et al. | Patent Number: 5877530

Process for forming MOS device in integrated circuit structure using cobalt silicide contacts as implantation media
Inventor: Tsai, et al. | Patent Number: 5874342

Alignment mark contrast enhancement
Inventor: Pasch, et al. | Patent Number: 5863825

Process for forming integrated circuit structure with metal silicide contacts using notched sidewall spacer on gate electrode
Inventor: Tsai, et al. | Patent Number: 5851890

Diffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making same
Inventor: Aronowitz, et al. | Patent Number: 5837598

Electrostatic discharge (ESD) structure and buffer driver structure for providing ESD and latchup protection for integrated circuit structures in minimized I/O space
Inventor: Wei, et al. | Patent Number: 5835986

Product resulting from selective deposition of polysilicon over single crystal silicon substrate
Inventor: Grider, et al. | Patent Number: 5818100

Method for eliminating peeling at end of semiconductor substrate in metal organic chemical vapor deposition of titanium nitride
Inventor: Zhao, et al. | Patent Number: 5789028

MOSFET device with improved LDD region and method of making same
Inventor: Kapoor | Patent Number: 5780350

Method of making a barrier layer for via or contact opening of integrated circuit structure
Inventor: Zhao, et al. | Patent Number: 5770520

Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures
Inventor: Rostoker, et al. | Patent Number: 5756395

Oxide formed in semiconductor substrate by implantation of substrate with a noble gas prior to oxidation
Inventor: Aronowitz, et al. | Patent Number: 5739580

Method for forming minimum area structures for sub-micron CMOS ESD protection in integrated circuit structures without extra implant and mask steps, and articles formed thereby
Inventor: Wei, et al. | Patent Number: 5728612

Integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate
Inventor: Yee, et al. | Patent Number: 5723896

Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device
Inventor: Aronowitz, et al. | Patent Number: 5717238

Oxide formed in semiconductor substrate by implantation of substrate with a noble gas prior to oxidation
Inventor: Aronowitz, et al. | Patent Number: 5707888

Wafer tray and ceramic blade for semiconductor processing apparatus
Inventor: Somekh, et al. | Patent Number: 5697748

Integrated circuit structure having reduced cross-talk and method of making same
Inventor: Pasch, et al. | Patent Number: 5689134

Ceramic protection for heated metal surfaces of plasma processing chamber exposed to chemically aggressive gaseous environment therein and method of protecting such heated metal surfaces
Inventor: Dornfest, et al. | Patent Number: 5680013

Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench
Inventor: Schinella, et al. | Patent Number: 5670425

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