Patent Attorney: Ishimaru; Mikio

...6

Semiconductor local interconnect and contact
Inventor: Yelehanka, et al. | Patent Number: 7119005

Method and apparatus for spectrum deconvolution and reshaping
Inventor: Zeng, et al. | Patent Number: 7113666

Characterizing distribution signatures in integrated circuit technology
Inventor: Wu, et al. | Patent Number: 7099789

Programmer/feeder system task linking program
Inventor: Dykins, et al. | Patent Number: 7096468

Semiconductor packages and leadframe assemblies
Inventor: Han, et al. | Patent Number: 7091596

Packaging for optoelectronic devices
Inventor: Kossives, et al. | Patent Number: 7091469

Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect
Inventor: Maszara | Patent Number: 7081655

Horizontal TRAM and method for the fabrication thereof
Inventor: Zheng, et al. | Patent Number: 7081378

Via/line inductor on semiconductor material
Inventor: Zhang, et al. | Patent Number: 7078998

Memory with improved charge-trapping dielectric layer
Inventor: Halliyal, et al. | Patent Number: 7074677

Integrated circuit with protected implantation profiles and method for the formation thereof
Inventor: Lai, et al. | Patent Number: 7067362

Stacked die packaging and fabrication method
Inventor: Chow, et al. | Patent Number: 7064430

Integrated circuit leadframe with ground plane
Inventor: Han, et al. | Patent Number: 7064420

Reduction of lateral silicide growth in integrated circuit technology
Inventor: King, et al. | Patent Number: 7064067

Method of forming wing gate transistor for integrated circuits
Inventor: Phua, et al. | Patent Number: 7056799

Memory wordline spacer
Inventor: Sahota, et al. | Patent Number: 7053446

Method for semiconductor wafer planarization by isolation material growth
Inventor: Sahota, et al. | Patent Number: 7052969

Low power pre-silicide process in integrated circuit technology
Inventor: Chiu, et al. | Patent Number: 7049666

Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy
Inventor: Verma, et al. | Patent Number: 7049201

Supervised automatic text generation based on word classes for language modeling
Inventor: Abrego, et al. | Patent Number: 7035789

Shallow junction semiconductor and method for the fabrication thereof
Inventor: Pelella, et al. | Patent Number: 7033916

Trenches to reduce lateral silicide growth in integrated circuit technology
Inventor: Chan, et al. | Patent Number: 7023059

Heterojunction bipolar transistor using reverse emitter window
Inventor: Verma, et al. | Patent Number: 7022578

Multi-level gate SONOS flash memory device with high voltage oxide and method for the fabrication thereof
Inventor: Zheng, et al. | Patent Number: 7015101

Selectable open circuit and anti-fuse element, and fabrication method therefor
Inventor: Chan, et al. | Patent Number: 7015076

Chip scale package with open substrate
Inventor: Shim, et al. | Patent Number: 7008820

Ultra-uniform silicides in integrated circuit technology
Inventor: Chiu, et al. | Patent Number: 7005376

Method of manufacturing different bond pads on the same substrate of an integrated circuit package
Inventor: Zhao, et al. | Patent Number: 7005370

Low stress sidewall spacer in integrated circuit technology
Inventor: Ngo, et al. | Patent Number: 7005357

Semiconductor package with passive device integration
Inventor: Chow, et al. | Patent Number: 7005325

Authorized user system using biological signature
Inventor: Edwards | Patent Number: 6996839

Integrated circuit with simultaneous fabrication of dual damascene via and trench
Inventor: Liu, et al. | Patent Number: 6995087

Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types
Inventor: Ghandehari, et al. | Patent Number: 6994939

Conformal barrier liner in an integrated circuit interconnect
Inventor: Woo, et al. | Patent Number: 6989604

Integrated circuit package
Inventor: Li, et al. | Patent Number: 6979907

Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers
Inventor: Avanzino, et al. | Patent Number: 6979903

Manufacturing a conformal atomic liner layer in an integrated circuit interconnect
Inventor: Lopatin, et al. | Patent Number: 6972254

Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth
Inventor: Verma, et al. | Patent Number: 6972237

Multi-silicide in integrated circuit technology
Inventor: Chiu, et al. | Patent Number: 6969678

Air pocket resistant semiconductor package system
Inventor: Dimaano Jr., et al. | Patent Number: 6969640

Semiconductor package for memory chips
Inventor: Chiang, et al. | Patent Number: 6963135

Semiconductor package with heat sink
Inventor: Su | Patent Number: 6956741

Multichip module package and fabrication method
Inventor: Shim, et al. | Patent Number: 6943057

Torch bump
Inventor: Jin, et al. | Patent Number: 6940169

Method for forming conductor reservoir volume for integrated circuit interconnects
Inventor: Marathe, et al. | Patent Number: 6939803

Double polysilicon bipolar transistor and method of manufacture therefor
Inventor: Verma, et al. | Patent Number: 6936519

Semiconductor solid phase epitaxy damage control method and integrated circuit produced thereby
Inventor: En, et al. | Patent Number: 6933579

Micro bar code and recognition system and method thereof
Inventor: Liu, et al. | Patent Number: 6932272

Method and apparatus for providing controllable second-order polarization mode dispersion
Inventor: Zeng | Patent Number: 6928201

Method of manufacturing a semiconductor package for a die larger than a die pad
Inventor: Ramakrishna | Patent Number: 6927479

Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact
Inventor: Li, et al. | Patent Number: 6924202

Multichip module
Inventor: Liu, et al. | Patent Number: 6919627

Self-aligned lateral heterojunction bipolar transistor
Inventor: Li, et al. | Patent Number: 6908824

System and method for processing tester information and visualization for parameter with multiple distributions in integrated circuit technology development
Inventor: Wu, et al. | Patent Number: 6907379

Semiconductor package with enhanced chip groundability and method of fabricating the same
Inventor: Wang, et al. | Patent Number: 6903441

Method and system for estimating exportation time
Inventor: Tsai, et al. | Patent Number: 6901416

Scalable extensible network test architecture
Inventor: Joo, et al. | Patent Number: 6898720

Plug-and-play interconnection architecture and method with in-device storage module in peripheral device
Inventor: Su, et al. | Patent Number: 6898653

Method using quasi-planar double gated fin field effect transistor process for the fabrication of a thyristor-based static read/write random-access memory
Inventor: Quek, et al. | Patent Number: 6897111

Manufacturing seedless barrier layers in integrated circuits
Inventor: Lopatin, et al. | Patent Number: 6893955

Method of manufacturing semiconductor local interconnect and contact
Inventor: Yelehanka, et al. | Patent Number: 6884712

Method of manufacturing a semiconductor memory with deuterated materials
Inventor: Kamal, et al. | Patent Number: 6884681

Heterojunction BiCMOS semiconductor
Inventor: Zheng, et al. | Patent Number: 6881976

Method for forming SAC using a dielectric as a BARC and FICD enlarger
Inventor: Yang, et al. | Patent Number: 6878622

Heat spreader anchoring and grounding method and thermally enhanced PBGA package using the same
Inventor: Shim, et al. | Patent Number: 6875634

Testing multiple levels in integrated circuit technology development
Inventor: Steffan, et al. | Patent Number: 6875560

Digital subscriber line access and network testing multiplexer
Inventor: Chong | Patent Number: 6873685

Determination of nonphotolithographic wafer process-splits in integrated circuit technology development
Inventor: Erhardt, et al. | Patent Number: 6864107

Stacked semiconductor packages and method for the fabrication thereof
Inventor: Shim, et al. | Patent Number: 6861288

Method of semiconductor via testing
Inventor: Marathe | Patent Number: 6858511

Method for fabricating semiconductor packages, and leadframe assemblies for the fabrication thereof
Inventor: Han, et al. | Patent Number: 6858470

Method of manufacturing ESD protection structure
Inventor: Cai, et al. | Patent Number: 6855609

Integrated circuit package and manufacturing method therefor with unique interconnector
Inventor: Li, et al. | Patent Number: 6855573

Dual silicon-on-insulator device wafer die
Inventor: Cha, et al. | Patent Number: 6849928

Thyristor-based SRAM and method for the fabrication thereof
Inventor: Quek, et al. | Patent Number: 6849481

Data input method and device for a computer system
Inventor: Shen | Patent Number: 6848083

3-D spiral stacked inductor on semiconductor material
Inventor: Sia, et al. | Patent Number: 6841847

Manufacturing an integrated circuit with low solubility metal-conductor interconnect cap
Inventor: Wang, et al. | Patent Number: 6841473

ESD protection structure
Inventor: Cai, et al. | Patent Number: 6835985

System for semiconductor package with stacked dies
Inventor: Hur, et al. | Patent Number: 6833287

Method of fabricating BGA packages
Inventor: Pu, et al. | Patent Number: 6830957

Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits
Inventor: Hellig, et al. | Patent Number: 6828240

Color correcting and ambient light responsive CRT system
Inventor: Cooper | Patent Number: 6819306

Method of simultaneous display of die and wafer characterization in integrated circuit technology development
Inventor: Erhardt, et al. | Patent Number: 6815233

Wafer pattern variation of integrated circuit fabrication
Inventor: En, et al. | Patent Number: 6812550

Manufacturing and carrier system with feeder/programming/buffer system
Inventor: Bolotin | Patent Number: 6807727

Semiconductor memory with shadow memory cell
Inventor: McGee, et al. | Patent Number: 6807107

Liner for semiconductor memories and manufacturing method therefor
Inventor: Ngo, et al. | Patent Number: 6803265

Wordline latching in semiconductor memories
Inventor: Gieseke, et al. | Patent Number: 6798712

Method for determining pore characteristics in porous materials
Inventor: Ulfig, et al. | Patent Number: 6791081

System and method for monitoring server host operation
Inventor: Wen, et al. | Patent Number: 6782352

Serial unit identification
Inventor: Chong | Patent Number: 6775726

Heat spreaders, heat spreader packages, and fabrication methods for use with flip chip semiconductor devices
Inventor: Shim, et al. | Patent Number: 6775140

Memory wordline spacer
Inventor: Sahota, et al. | Patent Number: 6773988

Method for semiconductor wafer planarization by CMP stop layer formation
Inventor: Sahota, et al. | Patent Number: 6770523

Processing tester information by trellising in integrated circuit technology development
Inventor: Shetty, et al. | Patent Number: 6766265

Via-sea layout integrated circuits
Inventor: Park, et al. | Patent Number: 6765296

Testing system and method of operation therefor including a test fixture for electrical testing of semiconductor chips above a thermal threshold temperature of an interlayer dielectric material
Inventor: Yao, et al. | Patent Number: 6762613

Ion implantation with improved ion source life expectancy
Inventor: Ng, et al. | Patent Number: 6756600

Via/line inductor on semiconductor material
Inventor: Jiong, et al. | Patent Number: 6750750

...6