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					ITRS 2004-FEP Updates and Plans
    By J. Butterbaugh & C. Osburn,
       US FEP TWG Co-chairs
           San Francisco, CA
            July 12-14, 2004




                  DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
Starting Materials/Plans & Updates

       H. Huff and M. Walden co-chairs




                     DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
     Starting Materials, 2004 Updates
• 2004 Table Updates:
      – Added long term years & requirements
      – Set introduction date of 450mm wafer to 2011 (colored
        red)
      – Made editorial corrections to table footnotes
      – Made changes to table color coding protocol
   Meaning and Color Coding of Left Box                                 Meaning and Color Coding of Right Box
       Technology Requirements Value and                                        Metrology Readiness Capability
    Supplier Manufacturing Capability by Color                                               by Color
 Manufacturable solutions exist, and are being optimized               Manufacturable solutions exist, and are being optimized
          Manufacturable solutions are known                                    Manufacturable solutions are known
       Manufacturable solutions are NOT known                                Manufacturable solutions are NOT known




                                                           DRAFT - NOT FOR PUBLICATION       14 July 2004 – ITRS Summer Conference
                  Potential Solutions: 2004 Update
            Change SOI to clear colorization in 2004 and cross-hatched shading in
                    2006 to ensure consistency with commercial reality
                                       2003      2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018
      First Year of IC Production                                                                                                                                                        2019
                                      10 0 n m   9 0 nm    8 0 nm   7 0 nm   6 5 nm   5 7 nm   5 0 nm   4 5 nm   4 0 nm   3 5 nm   3 2 nm   3 0 nm   2 5 nm   2 2 nm   2 0 nm   18 n m



300m m Leading Edge
Materials Selection
   Defect Engineered
   CZ Wafers include:                      CZ Wafers
    • P/P+ and P/P++ epi                  Defect-engineered
    • P/P- epi                               CZ Wafers
    • Annealed Wafers
    • Slow pull/slow cool
                                                               Emerging Materials
                                                  (Strained materials/layers, high resistivity, etc.)
   SOI includes:
    • Bonded Wafers
    • SIMOX Wafers                     SOI          SOI
                                      Wafers       Wafers
    • Selective SOI areas
      w ithin the IC chip

                                         450 mm                                450 mm                                                                450 mm
Wafer Diam eter

                                                                                                                            675 mm                                     675 mm
                                       Alternatives to large-         (Includes novel substrates
                                        Diameter Si Wafers           and new circuit approaches)

Site Flatness
                                         Double-sided Polish

                                                           New                                  New              New Technology (Includes CMP; Orientation Dependent Etch;
                                                          Tech-                                Tech-             Localized Etch; Localized Deposition + blanket etch or CMP;
                                                          nology                               nology            Blanket layer + blanket etch or CMP)


This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution.
Research Required
Development Underway
Qualification / Pre-Production
Continuous Improvement


Work-in-Progress--Do Not Publish



                                                                                                                 DRAFT - NOT FOR PUBLICATION                                      14 July 2004 – ITRS Summer Conference
        Starting Materials 2005 Plans
• Review killer defect particle size (=1/2 technology node
  dimension)
• Conduct new IDM surveys to establish 2005 requirement:
   –   Wafer Orientation(s) and tolerances
   –   Strained Silicon
   –   200 & 300mm backside particles, texture, and edge roll-off
   –   SOI active layer thickness and tolerance for Fully Depleted
       Devices
• Review wafer edge profile and edge roll-off for immersion
  lithography
• Review site flatness requirements for consistency with
  Lithography requirements
• Expand requirements tables for SOI and other emerging
  materials.

                                  DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
   Surface Preparation
J. Barnett and K. Reinhardt co-chairs




                 DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
                  Surface Preparation
             2004 Update - Was / Is Analysis
      Tables 70a and 70b

    • Fill in Table 70b for added years: 2011, 2014, 2017
    • Back Surface Particles – Plan to add metrics: Survey in Progress

      Footnotes for Tables 70a and 70b
• Note [D] - rewrite when Back Surface metrics are established from survey
•   Note [E] - rewrite when Back Surface metrics are established from survey
•   Note [F] - Clarify classification of “Critical GOI” and “Critical Other” metals
•   Note [I] - Clarify basis for Surface Oxygen metrics
•   Note [J] - Plan to reference TI publication (pending) on the effects of surface
    roughness




                                              DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
                       Tables 70a/70b Footnote [I]
      Surface Preparation Technology Requirements—Long-term
      Front Surface Particles


      Year of Production                            2010    2011     2012    2013     2014    2015        2016     2017      2018    Driver

      Technology Node                               hp45                     hp32                         hp22
WAS   DRAM ½ Pitch (nm)                              45      40       35       32      28         25       22        20       18       D½

      Front surface particle

WAS
       Killer defect density, Dp Rp (#/cm2) [A]     0.025             0.02   0.025            0.02        0.014              0.022     D½
IS                                                          0.016                    0.016                         0.017

WAS    Critical particle diameter, dc (nm) [B]      22.5              17.5     16             12.5          11                 9       D½
IS                                                          20                         14                            10

WAS    Critical particle count, Dpw (#/wafer) [C]    86               155     195                 155      106                168      D½
IS                                                          123.3                     123.1                         133.4




                                                                    DRAFT - NOT FOR PUBLICATION         14 July 2004 – ITRS Summer Conference
        Interconnect Surface Preparation
        2004 Update - Was / Is Analysis
  Tables 83a and 83b
• Fill in Table 83b for added years: 2011, 2014, 2017
• Back Surface and Edge Particles – Plan to add metrics: Survey in Progress
• Maximum Dielectric Constant Shift – Combine Rework, Strip, and Clean
   Footnotes for Tables 83a and 83b
• Note [D] - rewrite when Back Surface metrics are established from survey
• Note [E] - rewrite when Back Surface metrics are established from survey
• Note [F] - rewrite when Edge metrics are established from survey
   Tables 64
• Wet cleaning chemistry potential solutions extending until hp32/1013
• Addition of pore sealing details – potential methodologies and timelines




                                         DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
                                                   Table 83a and b
      Interconnect Surface Preparation Technology Requirements
      —Near-term Requirements (shown)
                                 Year of Production                            2003    2004    2005     2006   2007     2008      2009     Driver
                                   Technology Node                                     hp90                    hp65
       DRAM ½ Pitch (nm)                                                       100      90      80       70     65       57        50       D½
       MPU / ASIC ½ Pitch (nm)                                                 107      90      80       70     65       57        50        M
       MPU Printed Gate Length (nm)                                             65      53      45       40     35       32        28        M
       MPU Physical Gate Length (nm)                                            45      37      32       28     25       22        20        M
       Wafer diameter (mm)                                                     300     300      300     300    300       300      300     D ½, M
       Wafer edge exclusion (mm)                                                2       2        2       2      2         2        2      D ½, M
       Cleaning Effects on Dielectric Material
Was    Maximum Dielectric Constant Increase due to Strip + Clean [L]           4.00%   2.50%   2.50%   2.50%   2.50%    2.50%    2.50%       M
Was    Maximum Dielectric Constant Increase Due to Rework [L]                  4.00%   2.50%   2.50%   2.50%   2.50%    2.50%    2.50%       M

Is     Maximum Dielectric Constant Increase Due to Rework, Strip + Clean [L]   4.00%   2.50%   2.50%   2.50%   2.50%    2.50%    2.50%       M

       Maximum Effect on Dielectric Critical Dimenstion due to Strip + Clean
                                                                               2.50%   2.50%   2.50%   2.50%   2.50%    2.50%    2.50%       M
       [M]




        Dielectric Constant Delta: Take into Account Total Clean Process




                                                                                 DRAFT - NOT FOR PUBLICATION    14 July 2004 – ITRS Summer Conference
                         Plans for 2005
• Front Surface Particles / Roughness / Material Loss
   – Work with YE to corroborate yield models
   – Develop model and add metrics for removal efficiency
• Back Surface Particles
   – Develop model for back surface particles to support empirical metrics
• Carbon/Oxygen
   – Establish requirements for high-k gate dielectrics
• Metals/Mobile Ions
   – Establish requirements for high-k gate dielectrics
• Interconnect Surface Preparation
   – Continue to work with Interconnect TWG
   – Establish requirement/potential solutions for pore sealing
• YE-WECC Cross-TWG Interaction
   – Continue to work with YE-WECC to set metrics for UPW/Chemical/Gas
     purity


                                    DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
Critical Dimension Etch
  G. Smith and Y. Kim co-chairs




               DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
                                                           2004 Updates
        • Introduce gate etch technical requirements for new
          long term years-2011,2014, 2017
WAS Gate etch bias (nm) [D]                                          7.1              6        5               4          3.6              3      MPU/ASIC
 IS                                                                  7      7         6        5       5       4           4       3       3
WAS L gate 3  variation (nm) [E]                                    1.8             1.4       1.3             1          0.9             0.7     MPU/ASIC

 IS                                                                  1.8    1.6      1.4       1.3    1.1      1          0.9     0.8     0.7
WAS Total allowable lithography 3  (nm) [ F]                       1.61             1.25     1.16            0.89        0.8             0.63    MPU/ASIC
 IS                                                                 1.61   1.43      1.25     1.16    0.98    0.89        0.80    0.72    0.63
    Total allowable etch 3  (nm), including photoresist trim and
WAS gate etch [F]                                                    0.8             0.63     0.58            0.45        0.4             0.31    MPU/ASIC
 IS                                                                 0.80   0.72      0.63     0.58    0.49    0.45        0.40    0.36    0.31
WAS Resist trim allowable 3  (nm) [G]                             0.46             0.36     0.34            0.26        0.23            0.18    MPU/ASIC
 IS                                                                 0.46   0.41      0.36     0.34    0.28    0.26        0.23    0.21    0.18
WAS Gate etch allowable 3  (nm) [G]                                0.66             0.51     0.47            0.37        0.33            0.26    MPU/ASIC
 IS                                                                 0.66   0.58      0.51     0.47    0.40    0.37        0.33    0.29    0.26
WAS CD bias between dense and isolated lines [H]                    15%            15%      15%            15%       15%            15%     MPU/ASIC
 IS                                                                 15%   15%     15%     15%    15%     15%       15%    15%    15%
    Minimum measurable gate dielectric remaining (post gate etch
WAS clean) [I]                                                       >0               >0       >0              >0         >0               >0     MPU/ASIC
 IS                                                                  >0     >0        >0       >0     >0       >0         >0      >0       >0




                                                                                DRAFT - NOT FOR PUBLICATION         14 July 2004 – ITRS Summer Conference
 Critical Dimension Etch-2005 Plans
• 2004 Questionnaire validates the notion that 10% 3 control of the
  final etched gate length is not currently achieved.
    – Current “Red Walls” for both lithography and Etch
• Problem worsens with further scaling of gate length
    – Variance contributions do not scale with gate length
• 2004 Questionnaire also clarified current lithography and etch
  practices that are used to produce leading edge gate lengths
• 2005 plans include:
    – Collaborate with Lithography TWG to re-allocate variance budgets to
      be more consistent with industry practice, and develop new etch
      requirements based on this allocations.
    – Collaborate with lithography, PIDS, and design TWG’s to identify
      ameliorating strategies and requirements.




                                    DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
THERMAL AND THIN FILM
    Updates/Plans

  C. Osburn and H. Huff co-chairs




                DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
                      2004 Updates
   Explanations Added in Footnotes
         - Allowable Gate Leakage Taken as 10/3 and 1/3 of Device Off-
         State
         - Leakage for High Performance and Low Power Application
         Respectively
         - Emphasis that Gate Leakage Spec is Valid for All Biasing
         Modes of Transistor
         - Recognition that Switch to High k and Metal Gates is Likely to
         Occur Together, Rather than Staggered

   Editorial Corrections of Errors in 2003 Roadmap
       - Consistency in SiON Leakage (1/30 vs. 1/100 of Oxide)
       - Specification of Temperature Corresponding to Leakage Spec
       - Removal of Reference to DRAM Transistor Leakage

   Requirements Values Generated and Added for 2011, 2014, and 2017




                                 DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
              2005 Roadmap Agenda
                  Gate Leakage
• Re-Examine Gate Leakage Specifications
   - Provide Rationale for Relationship of Gate Leakage Spec to Device
     Off-State Leakage (if any)
   - Consider Inverter Applications Which have Different Biasing
     Configurations and Involve Both NMOS and (Different Sized) PMOS
   - Involve PIDS and Circuit Design Communities


• Include Specifications on PMOS Leakage (with PIDS)
    - Including Observation that Area of PMOS Transistor is Larger
    - Requires Parallel Activity of PIDS




                                   DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
          2005 Roadmap Agenda
           Non-Classical CMOS
• Include Non-Classical CMOS Device Configurations
   - Single Gate FD SOI
   - FINFET
   - Tri- and Multi-Gate Devices

• Include Reqjuirements on Strained Layer Channels
   - Mobility Enhancement Required (PIDS)
   - Strain in Channel?, Thickness of Strained Layer?
        (with Starting Materials)
   - Non-Uniform Strain Requirements? (from Gate, STI)
   - Stress in Layers? (with Starting Materials)
   - Maximum Processing Temperatures? (with Doping)



                           DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
             2005 Roadmap Agenda
            Shallow Trench Isolation
•   Expand on Shallow Trench Requirements (as feasible)
    - Add Specification on n+ - p+ Spacing
    - Provide Models to Quantify Tradeoffs Between Trench
      Parameters, e.g., top rounding, bottom rounding,
      angle, recess, etc.




                            DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
Doping Updates/Plans
H. Gossmann and M. Ieong co-chairs




                DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
           2004 Doping Updates
• Generate Doping Requirements for years 2011, 2014,
  and 2017
• No other planned changes




                          DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
           2005 Doping Initiatives
• EOT, CET, and Poly-depletion
• Source/Drain Extension Parameters:
   – Lateral abruptness
   – Junction Depth
   – Sheet Resistance
• Contact Resistance
   – Bulk CMOS Devices
   – Non-classical CMOS Devices
• Achieve internal consistency of PIDS assumptions and Doping
  Processes
• Overall: Achieve Tighter coupling with PIDS




                                  DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
                         2005 Initiatives
•   EOT, CET and Poly Depletion
     – Achieve EOT requirements for gate dielectric that are consistent with PIDS
       requirements for CET, and are consistent with model based values for polysilicon
       depletion, channel quantum effects, and metal gates
•   Extension Lateral Abruptness
     – For bulk devices improve on existing simplistic scaling law (0.11Lg)
     – Generate requirements for non-classical CMOS devices
•   Extension Junction Depth
     – Review current scaling rule (0.55Lg) to take into account the effect of halo
       implants
     – Is dopant activation with negligible diffusion really required? Are alternate
       strategies (halo + offset spacer) viable?
     – Review Xj requirements for non-classical ultra thin body devices
•   Extension Sheet Resistance
     – Review impact on requirements by use of metal gate & strained silicon channels
     – Possibly develop listing of dopant doses and implant energies required for a given
       resistance and depth profile
     – Determine whether current PIDS allocation between parasitic resistance and
       capacitance is still appropriate, and impact on offset spacer requirements


                                          DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
           2005 Doping Initiatives
• Contact Resistance
   – Obtain better estimates for Bulk contact resistance
     requirements and required dopant concentrations
   – Review/upgrade requirements for non-classical CMOS devices
• Tighter coupling with PIDS
   – PIDS will extend bulk parameters by an additional two nodes
     to provide overlap with two nodes having non-classical devices
   – Assure that this does not result in unphysical demands on
     doping processes
   – Close the loop with PIDS




                                DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
    Memory Updates/Plans
DRAM Stack Capacitor- S. Sawada, M. Oda
  DRAM Trench Capacitor- M. Gutsche
    Flash Memory- M. Alessandri
         FeRAM-M. Kubota


                  DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
           Memory-2004 Updates
• DRAM
   – Added requirements for years 2011, 2014 & 2017
   – No other planned changes
• FeRAM
   – 2005 feature size changed from 0.13 to 0.15 
   – Add requirements for years 2011, 2014, 2017
• Flash
   – Add Requirements for years 2011, 2014, 2017
   – No other Changes Planned
   – Address differences in FEP and PIDS tables



                                DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference
              Memory-2005 Plans
• DRAM- revisit cell “a” factor forecast for Stack and
  Trench capacitors, and update requirements
• FeRAM- Review and update requirements to reflect
  technology changes
• Flash- A new Technology Driver?
   – A leading memory manufacturer has stated that Flash has
     become the technology driver
   – Will this become widespread?
   – Review the Flash requirements from this perspective, and
     ascertain impact on overall FEP difficult challenges.
• Add requirements for new memory devices
   – MRAM, SONOS, PCM, Floating Body, …


                               DRAFT - NOT FOR PUBLICATION   14 July 2004 – ITRS Summer Conference

				
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