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State Machine Design

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					State Machine Design

    Digital Electronics
        State Machine Design
This presentation will
• Define a state machine.
• Provide several examples of everyday items that
  are controlled by state machines.
• Illustrate the block diagram for a state machine.
• Review the design steps in the state machine
  design process.
• Provide an example of a simple state machine
  design.                                             2
Definition of a State Machine

State Machine
  A synchronous sequential circuit,
  consisting of a sequential logic section
  and a combinational logic section,
  whose outputs and internal flip-flops
  progress through a predictable
  sequence of states in response to a
  clock and other input signals.
                                             3
  Examples of State Machines
Many everyday devices are controlled by
state machines.

           Traffic Light

 Garage Door Numeric Keypad

         Vending Machine
                                          4
           State Machine Block Diagram



                  Input                             Output
                           ...   Memory




                                              ...



                                                             ...
                 Combo                              Combo          Output(s)
           ...




Input(s)                         Flip-Flops
                  Logic                              Logic




                   Clock




                                                                      5
  State Machine Design Steps
1. Create State Graph
2. Determine State Variables and Assign
3. Encode Outputs to States
4. Create State Transition Table
5. Write and Simplify Design Equations
6. Design Circuit
                                          6
    Anatomy of a State Graph
 Transition Arc
                                          Input Variable (X)
(For Input X=0)
                               X=0

                                     State (S0)
                     S0
 State “Bubble”     Qa Qb
                     0 0             X=1           Transition Arc
                   Y=0 & Z=1                      (For Input X=1)

State Variables
  (Qa & Qb)

Output Variables
    (Y & Z)                                                    7
 State Machine Design Example
Example:
   Design a state machine that will count out the last four digits of the
   phone number 585-476-4691.
                        “4”  “6”  “9”  “1”

    In addition to the clock input, this design has a second input called
    Enable (EN). Whenever the Enable is a logic (1), the outputs will
    continuously cycle through the four values 4,6,9,1. Whenever the
    Enable is a logic (0), the outputs will hold at their current values.

    For this design any form of combinational logic may be used, but
    the sequential logic must be limited to D flip-flops.

                                                C3
                 Enable          Phone          C2
                 Clock          Numbers         C1
                                                C0                          8
Step #1: Create State Graph
                         EN = 0


                   S0
          EN = 1                  EN = 1

                   “4”

 EN = 0                                      EN = 0
          S3                           S1

          “1”                          “6”


                   S2
          EN = 1                  EN = 1
                   “9”

                         EN = 0                       9
Step #2: Determine State Variables
and Assign
                             EN = 0


                     S0
            EN = 1   Qa Qb            EN = 1
                     0 0
                      “4”

  EN = 0                                          EN = 0
           S3                              S1
           Qa Qb                          Qa Qb
           1 1                            0 1
            “1”                            “6”


                     S2
                     Qa Qb
            EN = 1   1 0              EN = 1
                      “9”

                             EN = 0                        10
Step #3: Encode Outputs to States
                                         EN = 0


                                 S0
            EN = 1               Qa Qb              EN = 1
                                 0 0
                                  “4”
                           C3=0 C2=1 C1=0 C0=0
  EN = 0                                                          EN = 0
            S3                                            S1
           Qa Qb                                         Qa Qb
           1 1                                           0 1
            “1”                                           “6”
                           C3=1 C2=0 C1=0 C0=1
     C3=0 C2=0 C1=0 C0=1                          C3=0 C2=1 C1=1 C0=0
                                 S2
                                 Qa Qb
            EN = 1               1 0                EN = 1
                                  “9”

                                         EN = 0                            11
Step #3: Create State Transition Table

              Inputs                                            Outputs
 State




                               State
          Present      Input               Next              F/F             Encoded
           State                           State           Inputs            Outputs
         Qa    Qb      EN              Qa* Qb*         Da       Db      C3   C2   C1   C0
 S0      0      0       0      S0      0           0   0            0   0    1    0    0
 S0      0      0       1      S1      0           1   0            1   0    1    0    0
 S1      0      1       0      S1      0           1   0            1   0    1    1    0
 S1      0      1       1      S2      1           0   1            0   0    1    1    0
 S2      1      0       0      S2      1           0   1            0   1    0    0    1
 S2      1      0       1      S3      1           1   1            1   1    0    0    1
 S3      1      1       0      S3      1           1   1            1   0    0    0    1
 S3      1      1       1      S0      0           0   0            0   0    0    0    1

                                                                                            12
  Step #4: Write and Simplify
  Design Equations
Da  Qa Qb EN  Qa Qb EN  Qa Qb EN  Qa Qb EN
Da  Qa Qb EN  Qa EN  Qa Qb


Db  Qa Qb EN  Qa Qb EN  Qa Qb EN  Qa Qb EN
Db  Qb EN  Qb EN
Db  Qb  EN


C3  Qa Qb EN  Qa Qb EN  Qa Qb
C2  Qa Qb EN  Qa Qb EN  Qa Qb EN  Qa Qb EN  Qa
C1  Qa Qb EN  Qa Qb EN  Qa Qb
C0  Qa Qb EN  Qa Qb EN  Qa Qb EN  Qa Qb EN  Qa   13
Step #5: Circuit Design




                          14
Block Diagram / Schematic




                            15

				
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Jun Wang Jun Wang Dr
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