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Performance of Input and Output Selection Techniques on Routing Efficiency in Network-On-Chip: A Review

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Performance of Input and Output Selection Techniques on Routing Efficiency in Network-On-Chip: A Review Powered By Docstoc
					                                                             (IJCSIS) International Journal of Computer Science and Information Security,
                                                                                                            Vol. 9, No. 9, September 2011

             Performance of Input and Output Selection
                Techniques on Routing Efficiency in
                        Network-On-Chip

            Mohammad Behrouzian Nejad                                                       Amin Mehranzadeh
        Young Researchers Club, Dezfoul Branch                                     Department of Computer Engineering
               Islamic Azad University                                            Dezfoul Branch, Islamic Azad University
                    Dezfoul, Iran                                                              Dezfoul, Iran
          Mohamad.behrouzian@gmail.com                                                   Mehranzadeh@iaud.ac.ir


                                                          Mehdi Hoodgar
                                              Department of Computer Engineering
                                             Dezfoul Branch, Islamic Azad University
                                                          Dezfoul, Iran
                                                      Hoodgar@iaud.ac.ir



Abstract— Network-On-Chip (NOC) is a new paradigm to make                 the Internet. Data communications between segments of chip
the interconnections inside a System-On-Chip (SOC) system.                transferred through the network. In the most commonly found
Networks-On-Chip have emerged as alternative to buses to                  organization, a NOC is a set of interconnected switches, with
provide a packet-switched communication medium for modular                IP cores connected to these switches. NOCs present better
development of large Systems-On-Chip. The performance of                  performance, bandwidth, and scalability than shared busses
Network-On-Chip largely depends on the underlying routing                 [1-8].
techniques. Routing algorithm can be classified into three
categories, namely, deterministic routing, oblivious routing and
adaptive routing. Each routing algorithm has two constituencies:                              II.   NETWORK-ON-CHIP
output selection and input selection. In this paper we discuss                The idea of NOC is derived from large scale computer
about some input and output selection techniques which used by            networks and distributed computing. The Network-On-Chip
routing algorithms. Also, to provide new and more efficient               architecture provides the communication infrastructure for the
algorithms we examine the strengths and weaknesses of the                 resources. In this way it is possible to develop the hardware of
algorithm.                                                                resources independently as standalone blocks and create the
                                                                          NOC by connecting the blocks as elements in the network.
   Keywords: Network, System-On-Chip, Network-On-Chip,
Routing algorithm, Input selection, Output selection.                     Moreover, the scalable and configurable network is a flexible
                                                                          platform that can be adapted to the needs of different
                                                                          workloads, while maintaining the generality of application
                       I.    INTRODUCTION                                 development methods and practices. Fig.1 shows a mesh-
    As technology scales and chip integrity grows, on chip                based NOC, which consists of a grid of 16 cores. Each core is
communication is playing an increasing dominant role in                   connected to a switch by a network interface. Cores
System-On-Chip design. System-On-Chip complexity scaling                  communicate with each other by sending packets via a path
driven by the effect of Moore’s Law in Integrated Circuits are            consisting of a series of switches and inter-switch links. The
required to integrate from dozens of cores today to hundreds of           NOC contains the following fundamental components [9-13].
cores within a single chip in the near future. The NOC
approach has been recently proposed for efficient                             a) Network adapters implement the interface by which
communication in SOC designs. In order Network-On-Chip is                 cores (IP blocks) connect to the NOC. Their function is to
a new paradigm for System on Chip design. Increasing                      decouple computation (the cores) from communication (the
integration produces a situation where bus structure, which is            network).
commonly used in SOC, becomes blocked and increased                           b) Routing nodes route the data according to chosen
capacitance poses physical problems. Traditional bus in NOC               protocols. They implement the routing strategy.
architecture is replaced with a network which is a lot similar to




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                                                                                                    ISSN 1947-5500
                                                                         (IJCSIS) International Journal of Computer Science and Information Security,
                                                                                                                        Vol. 9, No. 9, September 2011
    c) Links connect the nodes, providing the raw                                    be classified into three categories, namely, deterministic
bandwidth. They may consist of one or more logical or                                routing, oblivious routing and adaptive routing. Deterministic
physical channels.                                                                   routing chooses always the same path given the source node
                                                                                     and the destination node. It ignores the network path diversity
                                                                                     and is not sensitive to the network state. This may cause load
                                                                                     imbalances in the network but it is simple and inexpensive to
                                                                                     implement. Besides, it is often a simple way to provide the
                                                                                     ordering of packets. Oblivious routing, which includes
                                                                                     deterministic algorithms as a subset, considers all possible
                                                                                     multiple paths from the source node to the destination node, for
                                                                                     example, a random algorithm that uniformly distributes traffic
                                                                                     across all of the paths. But oblivious algorithms do not take the
                                                                                     network state into account when making the routing decisions.
                                                                                     The third category is adaptive routing, which distributes traffic
                                                                                     dynamically in response to the network state. The network state
                                                                                     may include the status of a node or link, the length of queues,
               Figure 1. The typical structure of a 4*4 NOC
                                                                                     and historical network load information [17, 18]. In the NOC,
                                                                                     to route packets through the network, the switch needs to
                                                                                     implement a routing technique [9]. A routing technique witch
B. Topology in Network-on-Chip                                                       used in routing algorithms has two constituencies: output
    The job of the network is to deliver messages from their                         selection and input selection which describes in section D and
source to their designated destination. This is done by                              E.
providing the hardware support for basic communication
primitives. A well-built network, as noted by Dally and Towles                       D. Input Selection Technique
[14], should appear as a logical wire to its clients. An on-chip                         Multiple input channels may request simultaneously the
network is defined mainly by its topology and the protocol                           access of the same output channel, e.g., in fig.3 packets p0 of
implemented by it. Topology concerns the layout and                                  input_0 and p1 of input_1 can request output_0 at the same
connectivity of the nodes and links on the chip. Protocol                            time. The input selection chooses one of the multiple input
dictates how these nodes and links are used [12, 13]. In order                       channels to get the access. Two input selections have been used
Topology determines how the nodes in the network are                                 in NOC, first-come-first-served (FCFS) input selection and
connected with each other. In a multiple-hop topology, packets                       round-robin input selection. In FCFS, the priority of accessing
may travel one or more intermediate nodes before arriving at                         the output channel is granted to the input channel which
the target node. Regular multiple-hop topologies such as mesh                        requested the earliest. Round-robin assigns priority to each
and torus are widely used in NOCs. We can use different                              input channel in equal portions on a rotating basis. FCFS and
topologies for the optical data transmission network and the                         round-robin are fair to all channels but do not consider the
electronic control network respectively [15, 16]. Fig.2 shows                        actual traffic condition [9].
some kinds of topology which used in NOC.




 Figure 2. (a) 4-ary 2-cube mesh, (b) 4-ary 2-cube torus and (c) binary tree
                                                                                                   Figure 3. Block diagram of switch in NOC

C. Routing Algorithms                                                                    Dong Wu in [9] a new input selection technique presented
    Routing on NOC is similar to routing on any network. The                         which based on Contention Aware Input Selection (CAIS). The
routing techniques for NOC have some unique design                                   main idea behind CAIS is that when two or more input packets
considerations besides low latency and high throughput. Due to                       both desire the same output channel, the decision as to which
tight constraints on memory and computing resources, the                             packet should obtain the output is made based on upstream
routing techniques for NOC should be reasonably simple [5, 6,                        contention information. The aim of CAIS is to use contention
and 9]. The routing algorithm determines the routing paths the                       information to alleviate congestion [9, 19].
packets may follow through the network graph. It usually
                                                                                        In order, the basic idea of CAIS is to give the input
restricts the set of possible paths to a smaller set of valid paths.
                                                                                     channels different priorities of accessing the output channels.
In terms of path diversity and adaptively, routing algorithm can
                                                                                     The priorities are decided dynamically at run-time, based on




                                                                               126                              http://sites.google.com/site/ijcsis/
                                                                                                                ISSN 1947-5500
                                                              (IJCSIS) International Journal of Computer Science and Information Security,
                                                                                                             Vol. 9, No. 9, September 2011
the actual traffic condition of the upstream switches. More                scheme which is based on Odd-Even routing algorithm[10] and
precisely, each output channel within a switch observes the                combines deterministic and adaptive routing is proposed in
contention level (the number of requests from the input                    [22], where the switch works in deterministic mode when the
channels) and sends this contention level to the input channel             network is not congested, and switches to adaptive mode when
of the downstream switch, where the contention level is then               the network becomes congested. In the IV, V and VI we
used in the input selection. When multiple input channels                  describes some kinds of output selection techniques of
request the same output channel, the access is granted to the              deterministic routing, oblivious routing and adaptive routing
input channel which has the highest contention level acquired              which presented for NOC.
from the upstream switch. This input selection removes
possible network congestion by keeping the traffic flowing                     III.   IMPORTANT PROBLEMS IN ROUTING ALGORITHMS
even in the paths with heavy traffic load, which in turn
improves routing performance. Fig. 4 shows the algorithm of                    Many properties of the NOC are a direct consequence of
CAIS [9]. In CAIS an input channel which has lower CL                      the routing algorithm used. Among these properties we can
continuously competing with channels which have higher CL,                 cite the following [23]:
obviously will be defeated any time. The packets in this
channel won't be able to get their required output channel and                 a) Connectivity: Ability to route packets from any
face with starvation and this will cause the problem of                    source node to any destination node.
decreasing network efficiency. Thus, there is a starvation                      b) Adaptively: Ability to route packets through
possibility in this new input selection technique, because it              alternative paths in the presence of contention or faulty
performs input selection only based on the highest contention              components.
level (CL) and the channels with low CL have a little chance
for winning. So this input selection technique improved in [20],                c) Deadlock and live lock freedom: Ability to guarantee
which in addition to CL, another parameter with the name of                that packets will not block or wander across the network
AGE for every input channel is taken into consideration and                forever.
measure of priority will be a compound of CL+AGE. In this                       d) Fault tolerance: Ability to route packets in the
technique, the problem of starvation has been resolved.                    presence of faulty components. Although it seems that fault
                                                                           tolerance implies adaptively, this is not necessarily true. Fault
                                                                           tolerance can be achieved without adaptively by routing a
                                                                           packet in two or more phases, storing it in some intermediate
                                                                           nodes.
                                                                               A good routing algorithm should be avoidance from
                                                                           deadlock, live lock, and starvation. Deadlock may be defined
                                                                           as a cyclic dependency among nodes requiring access to a set
                                                                           of resources, so that no forward progress can be made, no
                                                                           matter what sequence of events happens. Live lock refers to
                                                                           packets circulating the network without ever making any
                                                                           progress towards their destination. Starvation happens when a
                                                                           packet in a buffer requests an output channel, being blocked
                                                                           because the output channel is always allocated to another
                                                                           packet [7, 20, and 23].

                                                                                      IV.    DETERMINISTIC ROUTING ALGORITHMS
                                                                               Many properties of the NOC are a direct consequence of
                                                                           the routing algorithm used. The XY algorithm is deterministic.
                                                                           Flits are first routed in the X direction, until reaching the Y
          Figure 4. Pseudo VHDL code of the CAIS algorithm                 coordinate, and afterwards in the Y direction. If some network
                                                                           hop is in use by another packet, the flit remains blocked in the
                                                                           switch until the path is released [5, 7].
E. Output Selection Technique
    A packet coming from an input channel may have a choice
                                                                                        V.    OBLIVIOUS ROUTING ALGORITHMS
of multiple output channels, e.g., in fig.2 a packet p0 of input_0
can be forwarded via output_0, output_1 and so on. The output              A. Dimension Order Routing
selection chooses one of the multiple output channels to deliver
the packet. Several switch architectures have been developed                  This routing algorithm routes packets by crossing
for NOC [5, 9, and 10], employing XY output selection and                  dimensions in increasing order, nullifying the offset in one
wormhole routing. The routing technique proposed in [21]                   dimension before routing in the next one. A routing example is
acquire information from the neighboring switches to avoid                 shown in Fig.5 Note that dimension-order routing can be
network congestion and uses the buffer levels of the                       executed at the source node, storing information about turns
downstream switches to perform the output selection. A routing




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                                                                                                     ISSN 1947-5500
                                                                    (IJCSIS) International Journal of Computer Science and Information Security,
                                                                                                                   Vol. 9, No. 9, September 2011
(changes of dimension) in the header [6]. This is the street-                 D. VALIANT Routing Algorithm
sign routing algorithm described above. Dimension-order                           The VALIANT routing algorithm guarantees optimal
routing can also be executed in a distributed manner. At each                 worst-case throughput by randomizing every traffic pattern
intermediate node, the routing algorithm supplies an output                   [26]. VALIANT randomly picks an intermediate node from
channel crossing the lowest dimension for which the offset is                 any node in the network and routes minimally from source to
not null.                                                                     intermediate node and then from the intermediate to the
                                                                              destination node. This is a non-minimal routing algorithm
                                                                              which destroys locality and hurts header latency, but
                                                                              guarantees good load balancing. It can be used if the worst-
                                                                              case throughput is the only critical measure for the network.
                                                                              IVAL (Improved Valiant’s randomized routing) is an
                                                                              improved version of the oblivious Valiant’s algorithm. It is a
                                                                              bit similar to turn around routing. On the algorithms first stage
                                                                              packets are routed to a randomly chosen point between the
                                                                              sender and the receiver by using an oblivious dimension order
                                                                              routing. The second stage of the algorithm works almost
                                                                              equally, but this time the dimensions of the network are gone
  Figure 5. Routing example for dimension-order routing on a 2-D mesh         through in reversed order. Deadlocks are avoided in IVAL
                                                                              routing by dividing router’s channels to virtual channels. Full
                                                                              deadlock avoidance requires a total of four virtual channels
B. O1TURN Routing Algorithm
                                                                              per one physical channel.
    An oblivious routing algorithm (O1TURN) for 2-D mesh
networks has been described in [24]. O1TURN performs well
in the three main criteria as defined in their paper –
                                                                                          VI.   ADAPTIVE ROUTING ALGORITHMS
minimizing number of hops, delivering near optimal worst-
case and good average-case throughput, and allowing a simple                  A. Q-Routing
implementation to reduce router latency. According to the
authors, existing routing algorithms optimize some of the                        The functionality of a Q-routing algorithm is based on the
above mentioned design goals while sacrificing the others.                    network traffic statistics. The algorithm collects information
The proposed O1TURN (Orthogonal One-TURN) algorithm                           about latencies and congestions and maintains statistics about
addresses all three of these issues. O1TURN allows each                       network traffic. The Q-routing algorithm does the routing
packet to traverse one of two dimension-ordered routes (X                     decisions based on these statistics [27, 28].
first or Y first) by randomly selecting between the two
options. It is an interesting 2-D extension to the Randomized                 B. Odd-Even Routing Algorithm
Local Balanced routing (RLB) algorithm utilized in ring                           The odd-even adaptive routing algorithm was proposed by
topologies [6].                                                               Chiu [10]. In his paper on the odd-even turn model. The model
                                                                              shows how selectively restricting the directions routing turns
C. ROMM Routing Algorithm                                                     are permitted to take provides the resource ordering needed to
    ROMM is a class of Randomized, Oblivious, Multi-phase,                    ensure that the routing algorithm remains deadlock free. The
Minimal routing algorithms [25]. For a large range of traffic                 odd-even routing algorithm prohibits even column routing
patterns ROMM is superior to DOR since it allows minimal                      tiles from routing east to north and east to south while
routing with some load balancing. ROMM randomly chooses                       prohibiting odd column routing tiles from routing north to
an intermediate node in the minimal rectangle between the                     west and south to west. Among adaptive routing algorithms
source and destination nodes, and then routes packets through                 without virtual channel support [7], the odd-even scheme
the intermediate node using DOR. The simplicity and good                      routes in a more evenly distributed fashion across the network.
average-case performance of ROMM make it a desirable                          A minimal route version of odd-even was selected to ensure
algorithm for systems where average-case throughput is                        the network doesn’t live lock and also to minimize energy
important. However, ROMM fails to provide good worst-case                     consumption.
throughput since source/destination pairs can create additional
congestion in channels not in the row and column of source                    C. DyAD Routing Algorithm
and destination nodes. Although the worst-case throughput is                      The acronym DyAD stands for: Dynamically switching
undesirably low, in practice it does not occur very frequently.               between Adaptive and Deterministic routing modes. The
In fact people were generally unaware of the exact worst case                 intention of the DyAD routing scheme Hu [22] is to propose a
traffic pattern until an analytical approach 4 for calculating                new paradigm for the design of a Network-On-Chip router that
worst case throughput was described in [6]. Therefore,                        allows the NOC routing algorithm to exploit the advantages of
ROMM is a popular choice for networks where the worst-case                    both deterministic and adaptive routing. As such, DyAD is
throughput is not critical.                                                   presented as a hybrid routing scheme that can perform either




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                                                                                                        ISSN 1947-5500
                                                            (IJCSIS) International Journal of Computer Science and Information Security,
                                                                                                           Vol. 9, No. 9, September 2011
adaptive or deterministic routing to achieve best possible                                          VII. CONCLUSIONS
throughput. With the DyAD hybrid routing scheme, the                         Network-On-Chip is a technology of future on System on
network continuously monitors its local network load and                 Chip implementations. Content as can be concluded that the
makes the choice of whether to use an adaptive or                        input and output selection techniques which used in routing
deterministic routing mode based on local network load. When             algorithm, significant impact on Network on Chip
the network is not congested a DyAD router works in a                    performance is better. This paper shows importance of routing
deterministic mode and thus can route with the low latency               algorithm in rate of delays in the routing and network better
that is facilitated by deterministic routing. When the network           performance and yet, some of the most popular and efficient
becomes congested, a DyAD router switches to routing in                  routing algorithms which proposed for Network on Chip,
adaptive mode to avoid routing to congested links by                     introduced and examined. Most existing algorithms, despite
exploiting other less congested routes. The authors                      significant improvements in reducing the average latency and
implemented one possible variation of the DyAD hybrid                    network performance have improved. But still the more
scheme that employs two flavors of the odd-even routing                  defects and incomplete to improve performance of Network on
scheme, one flavor as a deterministic scheme and one flavor as           Chip, it is felt. The paper also examines the strengths and
an adaptive routing scheme. By measuring how full local                  weaknesses of the algorithms, to provide new and more
FIFO queues are, a router may switch between deterministic               efficient algorithms can be useful. The some outlines and
and adaptive modes. Further, the DyAD scheme proposed is                 features of the routing algorithms presented above are listed in
shown to be deadlock and live lock free in the presence of the           Table. I.
mixture of deterministic and adaptive routing modes.
Performance measurements are reported that highlight the
advantages of this hybrid approach. Measurements are                        TABLE I.        OUTLINES AND FEATURES OF ROUTING ALGORITHMS[6]
reported for several permutation traffic patterns as well as a               Algorithm       Outlines                            Features
real world multimedia traffic pattern. Evidence is presented                 XY              routing first in X and then in      simple,      loads
that the additional resources required to support a hybrid                                   Y dimension                         network deadlock-
routing scheme are minimal.
                                                                                                                                 and live lock free
                                                                             DOR             routing in one dimension at a       Simple
D. Hot-Potato Routing
                                                                                             time
    The hot-potato routing algorithm routes packets without                  Q-Routing       Statistics based routing            uses the best path
temporarily storing them in router’s buffer memory. Packets                  Odd-Even        Turn model                          Deadlock free
are moving all the time without stopping before they reach
                                                                             DyAD            Dynamically      Deterministic      uses the best path
their destination. When one packet arrives to a router, the
                                                                                             and Adaptive mode
router forwards it right away towards packet’s receiver but if
there are two packets going to same direction simultaneously,                2TURN           slightly determined                 Efficient
the router directs one of the packets to some other direction.               Hot-potato      routing  without           buffer   cheap, sometimes
This other packet can flow away from its destination. This                                   memories                            misrouting
occasion is called misrouting. In the worst case, packets can be             IVAL            Improved turnaround routing         Uses efficiently
misrouted far away from their destination and misrouted                                                                          whole network
packets can interfere with other packets. The risk of
misrouting can be decreased by waiting a little random time
before sending each packet. Manufacturing costs of the hot-                                             REFERENCES
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[16] T.Ye, L. Benini, and G. De Micheli, "Packetization and routing analysis                Mohammad Behrouzian Nejad Was born in Dezful, a city in
     of on-chip multiprocessor networks", Journal of Systems Architecture,                  southwestern of Iran, in 1990. He is currently Active Member of Young
     vol. 50, pp. 81-104, 2004.                                                             Researchers Club (YRC) and a B.Sc student at Islamic Azad University,
[17] Z. Lu, "Design and Analysis of On-Chip Communication for Network-                      Dezful Branch, Dezfoul, Iran. His research interests are Computer
     on-Chip Platforms", Department of Electronic, Computer and Software                    Networks, Information Technology and Data Mining.
     Systems School of Information and Communication Technology Royal
     Institute of Technology (KTH) Sweden, 2007.                                            Amin Mehranzadeh was born in Dezfoul, Iran, in 1979. He received a
[18] W. J. Dally and B. Towles. "Principles and Practices of Interconnection                B.Sc. degree in computer architecture from Azad University of Dezful,
     Networks", Morgan Kaufman Publishers, 2004.                                            Khuzestan, Iran in 2002 and a M.Sc. degree in computer architecture
[19] E.Chron, G.Kishinevsky, B.Nefcy, N.Patil," Routing Algorithms for 2-D                  systems from Azad university of Markazi, Arak, Iran in 2010. He is
     Mesh Network-On-Chip Architectures" http://www.cva.stanford.edu,                       currently teaching in the department of Computer Engineering at the
     06/15/2011.                                                                            Azad University of Dezful, Iran. His research interests include Network
                                                                                            on Chip (NOC) and simulation of Routing Algorithms.
[20] E .Behrouzian-Nejad, A. Khademzadeh , "BIOS:A New Efficient Routing
     Algorithm for Network on Chip", journal of Contemporary Engineering
     Sciences, Vol. 2,no. 1, 37 – 46, 2009.                                                 Mehdi Hoodgar was born in Dezfoul, Iran, in 1978. He received a B.Sc.
[21] E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. Van                           degree in computer architecture from Azad University of Dezful,
     Meerbergen, P. Wielage, and E. Waterlander, "Trade-offs in the design                  Khuzestan, Iran in 2002 and a M.Sc. degree in computer architecture
     of a router with both guaranteed and best-effort services for networks on              systems from Azad university of Khuzestan, Dezful, Iran in 2010. He is
     chip", IEEE Proceedings: Computers and Digital Techniques, vol. 150,                   currently teaching in the department of Computer Engineering at the
     pp. 294-302, 2003                                                                      Azad University of Dezful, Iran.
[22] J. Hu, R. Marculescu: "DyAD – Smart Routing for Networks-on-Chip",
     Proceedings, 41st Design Automation Conference, 2004.




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                                                                                                                     ISSN 1947-5500

				
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