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VIEWS: 12 PAGES: 24

									       ELG 4132 Tutorial
Principles & Application of VLSI Design



         VHDL DESIGN
   MULTI-MASTER SYSTEM
BUS AND SHARED MEMORY
         COMMUNICATION
                                          http://www.mcrlab.uottawa.ca
Presentation Outline

 • Overview
 • Bus Interconnection
    – Bus Structure
    – Bus Transaction
    – Bus Clocking
    – Bus Control
 • Example Buses
 • Design and Implementation
 • Summary


        (c) Multimedia Communications Research Laboratory (MCRLab)
                         http://www.mcrlab.uottawa.ca
Overview

 • Bus
   – A common electrical pathway connecting multiple
     devices
   – Serves as a shared communication link between the
     subsystems




         (c) Multimedia Communications Research Laboratory (MCRLab)
                          http://www.mcrlab.uottawa.ca
Bus Interconnection –                            Bus structure

                                                              Pentium System Organization
• Processor-memory
  buses
  – Short and high speed
  – Connects directly to the
    processor
• I/O Buses
  – Usually lengthy and slower
  – Wide range in the data
    bandwidth
• Backplane Bus
  – Allow processors, memory
    and I/O devices to co-exist

          (c) Multimedia Communications Research Laboratory (MCRLab)
                           http://www.mcrlab.uottawa.ca
Bus Interconnection –                            Bus transaction


• A typical bus transaction includes two parts:
  – Issuing the command by sending the address
  – Taking the action by transferring the data
      • a read transaction transfers data from memory
      • a write transaction writes data to the memory.
  – The devices that attached to a bus, actively starting the bus transactions
    are called masters; and the passive ones that responding to the masters
    are called slaves.
  – Operational rules must be set to ensure orderly data transfers on the bus
    -- bus protocol.
                                         Master issues command
                      Bus                                               Bus
                     Master                                            Slave
                                          Data can go either way

          (c) Multimedia Communications Research Laboratory (MCRLab)
                           http://www.mcrlab.uottawa.ca
Bus Interconnection –                            Bus Clocking


• Synchronous bus: has a line driven by a crystal oscillator,
  which includes a clock in the control lines.
• Asynchronous bus: dose not have master clock, which
  requires a handshaking protocol or interlocking mechanism.




          (c) Multimedia Communications Research Laboratory (MCRLab)
                           http://www.mcrlab.uottawa.ca
Bus Interconnection –                             Bus Control


• Arbitration-
   – In a modern computer system, more than one device need control the
     bus at the same time; but, only one device can successfully transmit over
     the bus at one time. The process of assigning control of the data transfer
     bus to a requester is called arbitration.

   – Designing a bus arbitration scheme is one of the most important issues
     in bus design; it usually try to balance two factors: bus priority and
     fairness.

   – Example: Daisy chain arbitration, Centralized parallel arbitration,
     Decentralized bus arbitration, Distributed arbitration.

   – ,     (c) Multimedia Communications Research Laboratory (MCRLab)
                            http://www.mcrlab.uottawa.ca
Bus Interconnection –                             Bus Control


• Centralized Parallel Arbitration-
   – Multiple bus request / grant signal lines can be independently provided
     for each potential master. In this scheme, each device has its own bus
     request / grant line, and the arbitration among potential masters is
     carried out by a central arbiter (central arbiter decide).

   – Very powerful and used in essentially all processor-memory buses and
     in high-speed I/O busses.




           (c) Multimedia Communications Research Laboratory (MCRLab)
                            http://www.mcrlab.uottawa.ca
Example Buses

• Historical and current-
  –   Unibus (PDP-11)
  –   Multibus (8086)
  –   VME bus (physical lab)
  –   ISA bus (PC/AT)                  Different buses have different
  –   EISA bus (80386)                 arbitration policies
  –   Nubus (macintosh)
  –   PCI bus (PCs)
  –   SCSI bus (workstations)
  –   SOC bus (system on-chip) : AMBA (AMD) and Avalon (Altera Nios)
  –   USB bus (modern PCs)
  –   Fire wire (consumer electronics)


           (c) Multimedia Communications Research Laboratory (MCRLab)
                            http://www.mcrlab.uottawa.ca
Example Buses (cont’)

• Example Buses
  (SOC bus)-
  – Designed for
    connecting on-chip
    processors and
    peripherals together
    into a System–On–a–
    Programmable Chip
    (SOPC)




         (c) Multimedia Communications Research Laboratory (MCRLab)
                          http://www.mcrlab.uottawa.ca
Example Buses (cont’)
• Example Buses (Traditional vs. Avalon)
  – Traditional
      • a single arbitrator controls communication between multiple bus
        masters and bus slaves. The arbitrator will grant a single master
        access to the bus after each potential master giving the control
        request. If more than one masters attempt to access the bus, the
        arbitrator allocates bus resources to a single master based on a
        fixed set of arbitration rules

      • Traditional systems have a bandwidth bottleneck because only one
        master can access the system bus at a time.


          (c) Multimedia Communications Research Laboratory (MCRLab)
                           http://www.mcrlab.uottawa.ca
Example Buses (cont’)

• Example Buses (Traditional vs. Avalon)
  – Avalon
     • The Avalon is simultaneous multi-master bus architecture which
       increases system bandwidth by eliminating this bottleneck because
       bus masters contend for individual slaves, not for the bus itself.

     • In Avalon, multiple masters can be active at the same time and can
       simultaneously transfer data to their slaves. Masters do not have to
       wait to access a target slave, as long as another master does not
       access the same slave at the same time.



         (c) Multimedia Communications Research Laboratory (MCRLab)
                          http://www.mcrlab.uottawa.ca
Example Buses (cont’)

• Example Buses (Traditional vs. Avalon)
             Avalon                                                  Traditional




        (c) Multimedia Communications Research Laboratory (MCRLab)
                         http://www.mcrlab.uottawa.ca
Lab#3 Design

• Objective
  – Design a simple multi-master bus system utilizing the shared memory
    message passing techniques and establish communication between
    several bus masters collaborating in performing an I/O task.


• Platform
  – Nios Development Hardware Board.
  – Quartus II software




          (c) Multimedia Communications Research Laboratory (MCRLab)
                           http://www.mcrlab.uottawa.ca
Lab#3 Design

• Central arbitration with independent requests and
  grants
  – Central arbiter carries out arbitration among multiple masters, and each
    master is connected to the central arbiter via its own independent bus
    request and grant lines.




          (c) Multimedia Communications Research Laboratory (MCRLab)
                           http://www.mcrlab.uottawa.ca
Lab#3 Design


– Consider the multi-master
  system and two bus masters
  (M0 and M1) use message
  passing through shared
  memory to collaborate in
  performing an I/O task, our task
  is simplified to lighting the
  LEDs on the Nios board one
  after the other. However, the
  two masters will collaborate in
  a round-robin fashion in driving
  the LEDs.




            (c) Multimedia Communications Research Laboratory (MCRLab)
                             http://www.mcrlab.uottawa.ca
Lab#3 Design
 M0 have higher priority and get control of
  the bus
 M0 checks the memory location
  associated with messages from M1
  (default value of this location should
  signal M0 to turn on the first LED)
 M0 proceeds by turning on LED0
 It then leaves a message for M1 in the
  memory and give up the control of the
  bus.
 The arbiter then passes control of the bus
  to M1
 Checks the message stored in memory
  from M0 to see which LED should be
  turned on next.
 M1 turns on the next LED (LED1) and
  leaves a message for M0.
             (c) Multimedia Communications Research Laboratory (MCRLab)
                              http://www.mcrlab.uottawa.ca
Lab#3- Design
• Memory Module Design

  – A memory block of two eight-bit words, which allows for a read or a write
    operation every clock cycle. Since the memory block consists of only two
    cells, a two-bit address bus should suffice to map the system. The Least
    Significant Bit (Address_bus(0)) of the address bus will decode which
    memory cell is to be accessed, and the Most Significant Bit
    (Address_bus(1)) of the bus will be used to choose between the memory
    block and the I/O buffer.




          (c) Multimedia Communications Research Laboratory (MCRLab)
                           http://www.mcrlab.uottawa.ca
Lab#3-Design (Memory Module)
                                           process(clk)
                                           begin
                                                            if(rising_edge(clk)) then
                                                                    if(reset = '1') then
                                                                         mem0 <= "11111110";
                                                                         mem1 <= "11111101";
                                                                    elsif(readEn = '1') then
                                                                         if(address_bus(0) = '0') then
                                                                                 data_out <= mem0;
                                                                         elsif(address_bus(0) = '1') then
                                                                                 data_out <= mem1;
                                                                         end if;
                                                                    elsif(writeEn = '1') then
                                                                         if(address_bus(0) = '0') then
                                                                                 mem0 <= data_in;
                                                                         else
                                                                                 mem1 <= data_in;
                                                                         end if;
                                                                    else
                                                                         data_out <= "ZZZZZZZZ";
                                                                    end if;
                                                            end if;
                                           end process;

      (c) Multimedia Communications Research Laboratory (MCRLab)
                       http://www.mcrlab.uottawa.ca
Lab#3-Design (Bus Master)
• State diagram
  – On reset, each master will initialize its Bus
  Request (BR) signal to logic low. In waiting-
  for-bus state BR is set high to
  issue a bus request signal to the arbiter, and
  the master waits for Bus Grant (BG) to arrive.
  Once the BG signal is issued by the arbiter,
  the master enters a memory-read state to
  read the message stored in the memory from the other master module.

  – Next, based on the read message, the master drives the I/O register. In
  the next state, a memory-write operation is performed to leave a message
  for the other master. Finally, a transition is made back to the initial state.

          (c) Multimedia Communications Research Laboratory (MCRLab)
                           http://www.mcrlab.uottawa.ca
Lab#3-Design (Bus Master)                                                  Which memory
                           :
                                                                           Cell?
• M0.vhd                   :
                                       when memory_read =>
                                                 BR <= '1';

                                                    address <= "00";
                                                      readmem <= '1';
                                                      writemem <= '0';
                                                      data_out <= "ZZZZZZZZ";

                                                                             Access memory
                                                      message := data_in;
                                                      next_state <= to_IO;

                                                                                 or I/O
                                          when to_IO =>
                                                      BR <= '1';
                                                      address <= "10";
                                                      readmem <= '0';
                                                      writemem <= '0';
                                                      data_out <= message;
                                                      next_state <= memory_write;
                                          when memory_write =>
                                                      BR <= '1';
                                                      address <= "01";
                                                      readmem <= '0';
                                                      writemem <= '1';
                                                      data_out(7 downto 1) <= message(6 downto 0);
                                                      data_out(0) <= message(7);
                                                      next_state <=complete;
                                          :
                                          :
                                          :
       (c) Multimedia Communications Research Laboratory (MCRLab)
                        http://www.mcrlab.uottawa.ca
Lab#3-Design (Bus Arbiter)




      (c) Multimedia Communications Research Laboratory (MCRLab)
                       http://www.mcrlab.uottawa.ca
Top Level Design

                      Bus master
                                                                      memory




    Clock
    divider

                                                                     I/O buffer

        Arbiter


        (c) Multimedia Communications Research Laboratory (MCRLab)
                         http://www.mcrlab.uottawa.ca
ありがとう!                       ‫متشکرم‬                            谢谢!

  (c) Multimedia Communications Research Laboratory (MCRLab)
                   http://www.mcrlab.uottawa.ca

								
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