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Modeling Finite-State Machines and ASM Charts Finite-state machines are widely used for modeling memory components, such as ﬂip-ﬂops, as well as controllers for synchronous datapath and register operations of a computer. Hence they have both theoretical and practical importance. A ﬁnite state machine (FSM) of Mealy type (or a Mealy machine) consists of a sextuple M = (Q, I, O, f, g, q0 ), where • Q is a ﬁnite set whose elements are called states • I is a ﬁnite set called the input alphabet • O is a ﬁnite set called the output alphabet • f : Q × I → S is a function that computes the next state of the machine as a function of the current state and the current input • g : Q × I → O is a function that computes the current output of the machine as a function of the current state and the current input • q0 ∈ S denotes the initial state of M . Note: if the function g depends on Q only, then M is called a Moore machine. Let I ∗ denote the set of (nonempty) strings over alphabet I, O∗ the set of strings over alphabet O, and Q∗ the set of strings over S. Given Mealy machine M = (Q, I, O, f, g, q0 ), there is a natural way of deﬁning a mappings 1. f ∗ I ∗ → Q∗ which maps an input string of length n ≥ 1 to a state string of length n + 1, and 2. g ∗ I ∗ → O∗ , which maps an input string of length n ≥ 1 to an output string of length n. In words, 1. f ∗ (s) denotes the sequence of states (starting with the initial state q0 ) M would enter if given the sequence of inputs s = s0 s1 , . . . , sn−1 , while 2. g ∗ (s) the sequence of outputs M would provide if given the sequence of inputs s = s0 s1 , . . . , sn−1 . As an example, the sequence of inputs might consist of machine instructions, while the sequence of outputs corresponding with it might be a sequence of datapath operations. 1 Example 1. Deﬁne a Mealy machine M whose input and output alphabets are both I = O = {0, 1} and whose g ∗ function maps binary string s to binary string p, where pi is the parity of string s0 s1 , . . . , si . Example 2. Same as Example 1, but now M is a Moore machine and g ∗ maps binary string s to binary string p, where pi is the parity of string s0 s1 , . . . , si−1 . 2 Comments on the implementation of ﬁnite state machines in hardware. Given a ﬁnite-state machine M . • the states of M are encoded using one or more synchronous ﬂip-ﬂops. • state transitions occur according to the rising of the clock edge • the next state and output is determined by sampling both the input and the current state at the next rising edge of the clock. Once the clock falls, both next state and output will be stabilized until the next rising edge. Mealy-Machine Architecture: Moore-Machine Architecture: 3 Specifying an FSM in Verilog When modeling an explicit ﬁnite state machine, we use two diﬀerent cyclic behaviors: 1. a level-sensitive behavior describing the combinational logic for the next state and output. The assignments are usually blocking. 2. an edge-sensitive behavior which synchronizes the state transitions. These assignments will be non-blocking. Example 3. This examples gives a explicit speciﬁcation of the Mealy machine from Example 1. module parityCheck(output reg P, input x, clk, reset); parameter S0= 1’b0, S1= 1’b1; reg state, nextState; always @(posedge clk, negedge reset) if(reset == 0) state <= S0; else state <= nextState; always @(state,x) begin case (state) S0: if(x == 0) begin nextState = S0; P=0; end else if(x == 1) begin nextState = S1; P=1; end S1: if(x == 0) begin nextState = S1; P=1; end else if(x == 1) begin nextState = S0; P=0; end endcase end endmodule How it works: 1. the nonblocking assignments are sampled ﬁrst before any assignments are made. For example, on the positive clock edge, the value of nextState would be sampled. 2. then the blocked assignments are executed 3. the non-blocking assignments are then completed by assigning the values that were determined by the sampling of the beginning of the time step 4 Algorithmic State Machines Algorithmic state machines are similar to ﬁnite state machines, yet are more expressive in that, during each state (i.e. clock cycle), register operations may be speciﬁed and performed during the transition (i.e. next positive clock transition) from the current state to the next state. An algorithmic-state-machine (ASM) chart consists of a set of n ≥ 1 blocks B1 , . . . , Bn . Each block B may be viewed as a directed simple graph that has three kinds of nodes: • state node (box). B has one state node which is symbolically represented as a rectangular box. The state node represents which state the system is in when block B is being executed. Within the box one may list one or more register operations that take place during the next rising clock edge when control passes from B to the next block/state. The state box has outdegree 1, and the edge leaving the state box may 1. loop back to itself, 2. be directed towards the state box of a diﬀerent block, or 3. be directed to a decision box within B. • binary decision node. A decision node is symbolically shaped like a diamond. Within the node is a binary predicate P which is a function of one or more net or register values. A binary decision node has two edges leaving it: one for each possible value of P . Edges leaving the decision node may 1. be directed towards the state box of any block, 2. another decision node within B, or 3. a conditional node. • conditional node (box). A conditional node is symbolically shaped like a rectangular box with rounded sides. Within the box are one or more register operations that take place during the next rising clock edge, on condition that execution passes through the box. Edges leaving the condtional box may 1. be directed towards the state box of any block, or 2. another decision node within B. Suppose that block B is being executed, and let n be a node of B. We say that execution passes through n iﬀ one of the following is true. 1. n is the state box for B 2. execution passes through a parent p of n, and p is not a decision node 3. execution passes through a decsision-node parent p of n, and the edge from p to n is consistent with the evaluation of predicate P , where P is the predicate associated with p 5 Example 4. Use an ASM chart to design an unsigned 8-bit counter which has the ability to reset, and count up by either one, two, or three. The synchronous inputs to the counter are a reset signal R, and a two-bit signal X which denotes the amount that the counter should increment by. The output is the value of the counter expressed as an 8-bit vector. 6 Example 5. Use the ASM chart to give an architectural view of the counter speciﬁed in the previous example. 7 Example 6. Use an ASM chart to design an 8×8 multiplier using one or more shift registers. 8

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posted: | 8/14/2009 |

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