Finite State Machines and Their Testing

							                 Finite State Machines

                            Experiment 4
                            Introduction



ECE 448 – FPGA and ASIC Design with VHDL   George Mason University
                        Sequence detector




ECE 448 – FPGA and ASIC Design with VHDL    2
Our Example

  Non-resetting detector of the sequence:
                                   (10)+ (11)


                                                sc
                                    sa     sb

    Input:           001010010111010110101010101100101
    Output:          000000000010000010000000000100000




ECE 448 – FPGA and ASIC Design with VHDL                 3
Our Example

 Joystick left = ‘1’
 Joystick right = ‘0’




ECE 448 – FPGA and ASIC Design with VHDL   4
 Moore State Diagram




ECE 448 – FPGA and ASIC Design with VHDL   5
 Moore Machine - ASM Chart




ECE 448 – FPGA and ASIC Design with VHDL   6
 Mealy State Diagram




ECE 448 – FPGA and ASIC Design with VHDL   7
 Mealy Machine - ASM Chart




ECE 448 – FPGA and ASIC Design with VHDL   8
 Questions?




ECE 448 – FPGA and ASIC Design with VHDL   9