The PCI bus by alicejenny


									The PCI bus
                     Main features
• coupling of the processor and expansion bus by means of a bridge,
• 32-bit standard bus width with a maximum transfer rate of 133
• expansion to 64 bits with a maximum transfer rate of 266 Mbytes/s,
     – PCI-64/66 532 Mbytes/s,PCI-X 64/133 1064 Mbytes/s
•   supporting of multi-processor systems,
•   burst transfers with arbitrary length,
•   supporting of 5 V and 3.3 V power supplies,
•   write posting and read prefetching,
•   multimaster capabilities,
•   operating frequencies from 0 MHz to a maximum of 33 MHz,
     – PCI-66 3.3V only, PCI-X 100MHz-133MHz
•   multiplexing of address and data bus reducing the number of pins,
•   supporting of ISA/EISA/MCA,
•   configuration through software and registers,
•   processor independent specification
Block diagram of a PCI bus system
          Processor/Main Memory System
 Copro-                                       Main
                CPU             Cache
 cessor                                      Memory

                        PCI                                    Motion
                       Bridge                                  Video
                                   PCI Bus

SCSI host     Interface to          LAN                    Graphics
 adapter     Expansion Bus         adapter                 adapter
                            Expansin Bus (ISA/EISA)

            Bus Slot    Bus Slot        Bus Slot    Bus Slot
Latest Generation of PCI Chipsets
• ACK64 # : acknowledge 64-bit transfer
• AD31-AD0: 32 address and data pins form the multiplexed PCI
  address and data bus
• C/BE3#-C/BE0#: command and byte-enable
• CLK: PCI clock signal
• DEVSEL#: device select
• GNT#: grant
• IDSEL: device select during configuration
• INTA#, INTB#, INTC#, INTD#: interrurpt signals
• IRDY#: initiator ready
• LOCK: defines an atomic access
• PAR: even parity for AD31-AD0 and C/BE3#-C/BE0#
• PERR#: parity error
•   PRSNT1#, PRSNT2#: indicate that an adapter is installed
•   REQ#: request signal to the bus arbitration unit
•   REQ64#: 64-bit transfer request
•   RST: resets all PCI units
•   SBO#: snoop backoff, indicates a hit to a modified cache line
•   SDONE: snoop done
•   SERR#: system error
•   STOP: target-abort
•   TCK, TDI, TDO, TMS, TRST#: JTAG boundary scan test signals
•   TRDY: target ready
•   64 bit expansion
    – AD63-AD32: 32 address and data pins form the expansion of the
      multiplexed PCI address and data bus
    – C/BE7#-C/BE4#
    – PAR64: even parity for the 64bit expansion
The PCI read transfer burst
The PCI write transfer burst.
• Bus Arbitration
  – Parallel arbitration
  – Hidden arbitration
  – Arbitration algorithm is not defined
  – Burst transfers
• Interrupts
  – INTA# activated
  – Data: interrupt vector
                    Bus Cycles
•   INTA sequence (0000)
•   special cycle (0001)
•   I/O read access (0010)
•   I/O write access (0011)
•   memory read access (0110)
•   memory write access (0111)
•   configuration read access (1010)
•   configuration write access (1011)
•   memory multiple read access (1100)
•   dual addressing cycle (1101)
•   line memory read access (1110)
•   memory write access with invalidation (1111)
            Configuration Address Space
                      31                 16 15                    0
                                                                      • Manufacturer ID
  64 Byte Header
                              Unit ID
                                                Manufacturer ID
                                                                         – allocated by PCI SIG
                                  Class code
                                    Header     Latency
                                                            CLS       • Unit ID, revision
                                                                         – identifies unit
192 Bytes Available

                                                                      • Class code
    for PCI Unit
                                  Base Address register

                                                                         – type of PCI unit
                             Expansion ROM Base Address
                      Max. Lat. Min. GNT       INT-Pin    INT-Line
 Status and Command Registers
• Status:                           • Command:
   –   PER: Parity error              – BEE: Fast back-to-back cycles
   –   SER: System error                (Back-to-Back Enable)
   –   MAB: Master abort              – SEE: SERR Enable
   –   TAB: Target abort received     – WC: Wait cycle control
   –   STA: Target abort signaled     – PER: Parity error (Parity Error
   –   DEVTIM: DEVSEL timing            Response)
        • 00=fast 01=medium           – VPS: VGA palette snoop
          10=slow 11=reserved         – MWI: Memory write access with
   – DP: Data parity error              invalidation
   – FBB: Fast back-to-back           – SC: Special cycle
     cycles                           – BM: Busmaster
     supported/unsupported            – MAR: Activate/deactivate
                                        Memory address area
                                      – IOR: Activate/deactivate I/O
                                        address area
           Accessing Configuration
               Address Space
• Configuration Mechanism #1
  – CONFIG-ADDRESS (0cf8h) and CONFIG-
    DATA (0cfch) registers are defined in the I/O
   31 30               24 23         16 15          11 10     8   7              2   1   0

            Reserved           Bus           Unit      Function       Register       Type

• Configuration Mechanism #2 (for PC
  – 4k I/O address range between c000h and
                  Base Address Registers
For Memory Address Space
31                                                16 15                       4   3     2   1     0

                                        Base Address                                    Type      0

For I/O Address Space
31                                                16 15                                 2   1     0

                                            Base Address                                          0

For Expansion ROM Address Space
31                                                16 15    11 10                        2   1     0

                             Base Address                          Reserved                 0

     • PRF: Prefetching not possible/prefetching possible
     • Type: Positioning type
          – 00=any 32-bit address, 01=less than 1M, 10=any 64-bit address,
     • AD: Address decoding and expansion ROM
       The PCI Express Bus
• Point to point protocol
  – x1, x2, x4, x8, x12, x16 or x32 point-to-point

• Differential Signaling
Low Cost PCI Express System
PCI Express High-End Server
      PCI Express Properties
• Packet Based Protocol
• Bandwidth and Clocking
  – 2.5 Gbits/sec/lane/direction
  – 8b/10b encoding
  – 250 Mbytes/sec/lane/direction
• Address Spaces
  – Memory
  – I/O
  – Configuration (extended from 256 Bytes to 4
    PCI Express Transactions
• Transactions
  – memory read / write
  – I/O read / write
  – configuration read / write
  – new transaction type: Message transactions
• Transaction Model
  – posted (split transaction communication)
  – non-posted
      PCI Express Properties
• Quality of Service (QoS)
  – deterministic latencies and bandwidth
• Traffic Classes (TCs)
  – TCs can move through the fabric with different
• Virtual Channels (VCs)
  – Each Traffic Class is individually mapped to a
    Virtual Channel
       PCI Express Properties
• Interrupt Handling
  – Virtual wires
• Power Management
  – device power states: D0, D1, D2, D3-Hot and D3-
     • D0 is the full-on power state
     • D3-Cold is the lowest power state.
  – Link power states: L0, L0s, L1, L2 and L3
• Hot Plug Support
• PCI Compatible Software Model
PCI Express Topology
Non-Posted Memory Read Originated
 by CPU and Targeting an Endpoint
PCI Express Device Layers
Transaction Layer Packets
 Electrical Physical Layer Showing
Differential Transmitter and Receiver
                    The SCSI Bus
•   SCSl: Small Computer Systems Interface
•   Maximum of eight units
•   Mainly hard disks, tape drives, optical drives
•   Asynchronous/synchronous protocol
•   Every unit is assigned a SCSI address
    – host adapter itself is also a SCSI unit
       • several PCs can share a common SCSI bus
    – max. 7 units
• Termination resistors are required
• SCSI drives are intelligent
    – data exchange is carried out without the slightest intervention
      from the CPU
    – split transactions
• BD(0)#-BD(7)#: data bits
• BD(P)#: parity bit
• BSY# (busy): the signal indicates whether the bus is
  currently busy.
• SEL# (select): the signal is used by the initiator to select
  the target device; on the contrary, the target may also
  use SEL to re-establish the connection to the initiator
  after a temporary release of the bus control.
• C/D# (control/data): the signal is exclusively controlled
  by the target, and indicates whether control information
  or data is present on the SCSI bus. An active signal (with
  a low level) denotes control information
• I/O# (input/output): the signal is exclusively controlled by the target
  device, and indicates the direction of the data flow on the data bus
  relative to the initiator. An active signal (with a low level) means a
  data transfer to the initiator.
• MSG# (message): the signal is activated by the target during the
  message phase of the SCSI bus.
• REQ# (request): the signal is activated by the target unit to indicate
  the handshake request during the course of a REQ/ACK data
• ACK# (acknowledge): the signal is activated by the initiator to
  indicate the handshake acknowledge during the course of a
  REQ/ACK data transfer.
• ATN# (attention): an initiator activates the signal to indicate the
  attention condition.
• RST (reset): an active signal resets all connected SCSI devices.
                 SCSI bus phases
• Bus-free
   – no SCSI unit is currently using and controlling the bus SEL# and BSY#
• Arbitration
   – unit activates BSY# and puts its SCSI-ID onto the data bus
   – After a short arbitration delay, if no other SCSI-ID with a higher priority
     is active then the unit may control the bus and activates SEL#
• Selection
   – initiator selects a target unit and advises the target to carry out certain
   – the I/O# signal is inactive
   – addressing by putting the OR-ed value of the SCSI-ID of the initiator
     and target to the bus
   – target activates BSY#
             SCSI bus phases
• Reselection
    – a target may re-establish the connection with
      the original initiator to continue the interrupted
•   Command
•   Data
•   Message
•   Status
      Operation of the SCSI Bus

               Bus free for
Initiator     other transfers    Target

                  SCSI Commands
     6-, 10-, 12- byte commands          • LUN: Logical Unit
         10-byte command                   Number
          Command Code
 LUN               Reserved        REL   • REL: relative
   Logical Block Address (MSB)             addressing
       Logical Block Address
                                         • Block addressing
       Logical Block Address
    Logical Block Address (LSB)
Transfer/Allocation/Parameter Length
Transfer/Allocation/Parameter Length
           Control Byte
     Evolution of SCSI Standards
• SCSI-I: 8-bit bus, asynchronous 3 Mbytes/s, 5 MHz
  synchronous mode 5 Mbytes/s
    – loosely specified
•   SCSI-II: the first real SCSI standard
•   Fast SCSI: 10 MHz synchronous mode 10 Mbytes/s
•   Wide SCSI: extended to 16 or 32 bit bus
•   Ultra SCSI: 20 MHz synchronous mode 20 Mbytes/s
•   Ultra Wide SCSI: 80 Mbytes/s
•   Ultra160 SCSI : 160 Mbytes/s, differential signaling
•   Ultra320 SCSI : 320 Mbytes/s
•   Optical
•   Serial

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