Design of a 4-MHz analog integrated CMOS transconductance-C by fdh56iuoui


									IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 4, AUGUST 1988                                                                                                                                            987

          Design of a 4-MHz Analog Integrated CMOS
              Transconductance-C  Bandpass Filter
                                              CHIN        S. PARK,             MEMBER, IEEE, AND ROLF                     SCHAUMANN,                FELLOW,          IEEE

   Abstract —Design             and evahratfon           of a continuous-time             eighth-order   fully   automatic       on-chip        method          [2]–[5],     [7], [8] against        fabrica-
integrated       CMOS        transeonductance-             C bandpass filter             for operation    at 4
                                                                                                                 tion      tolerances,     parasitic            effects,     and    component            drifts
MHz       is presented.       A phase-locked             loop (PLL)        for freqnency        tuning   and a
                                                                                                                 during operation.
four-point       amplitude-locking               loop    for    Q-factor       toning     at the reflection
zeros of the filter        are implemented.              The transfer        characteristics     were found        With these trade-offs                  in mind,         we discuss in this paper
to be essentially         within    specification              less than l-dB       passband attenuation,        the design       of an analog integrated                    eighth-order          bandpass
75-dB        stopband      attenuation           and S/N          ratio,    and 0.5-percent          harmouic    filter    for nominal         operation          at a band-center              frequency     of
distortion      for    0.5-VYP      signaf were observed.                  Offset    of the transconduc-
                                                                                                                 4 MHz,        with      800-kHz          btmdwidth           and 0.5-dB           passband
tances       was internally        controlled       by an offset-control              loop to less than 4
                                                                                                                 ripple.    The circuit        is built as a cascade of four second-order
mV. Also a temperature-insensitive                       transconductance            design and the noise
characteristics         of the filter        building    blocks are discussed.                                   sections,      each      using        only       capacitors        and         transconduc-
                                                                                                                 tances. DC offset of the transconductance     blocks is re-
                                                                                                                 duced to a few millivolts throughout the chip by a recently
                                        I.       INTRODUCTION                                                    proposed       [9] offset        zeroing        scheme. The circuit               uses fully
                                                                                                                 automatic        tuning  against deviations   in frequency                                  and
             NUMBER        of approaches have been discussed in the
             recent literature [1] –[6] for the design of continuous-
          (“analog”)               fully       integrated           filters.        Their      advantages
                                                                                                                 bandwidth        (Q) based on the “ master–slave”
                                                                                                                 e.g., [4]); it employs
                                                                                                                                                    a frequency-locking   loop to stabilize

                                                                                                                 the center frequency               and a four-point    magnitude locking
have         been pointed                  out     [2] and it has been                         shown     that
                                                                                                                 scheme to control              Q. Experimental              evaluation          of the final
continuous-time                    filtering            is competitive                  with     switched-
                                                                                                                 CMOS         chip     demonstrates              that,     except    for      a few minor
capacitor             (SC)      methods            even at low                 frequencies           [2], the
                                                                                                                 problems        caused        by unexpectedly               large processing            toler-
natural         SC domain.              For applications                   at higher frequencies,
                                                                                                                 ances, the filter        and the tuning                 methods    function        correctly.
SC filters            pose a number                     of challenging               design problems
caused by their                 sampled-data                   nature:       decreasing          amplifier
gain results in SC filters no longer being insensitive  to                                                                       II.     FILTER CIRCUIT AND STRUCTURE
parasitic   and the necessary high sampling   frequencies
increase the performance   requirements, such as settling                                                            The design is developed                    around       the recently         introduced
time,        placed        on the amplifiers.                     On the other hand, if the                      simple      linear     tunable      CMOS           transconductance              element [9]
sampling              frequency               is reduced             as far          as possible,         the    shown in Fig. 1. The device realizes
design          of     anti-aliasing               filters       becomes            increasingly          dif-
                                                                                                                                         g~ =     2keff       (VG1 + 1VG41– ‘VT)                            (la)
ficult,        requiring           greater          stability          and       higher         tolerances.
Because it is the performance                                  of the total jilter             system and        where
not just the intrinsic filter that is of relevance in practice, it
                                                                                                                                       XvT = vTn, + v~nq + IVTP2]+                   IJ’’TP41               (lb)
can be reasoned that staying in the continuous-time            do-
main, i.e., using all-analog                            filtering,         may be preferable. In                               i=~,.   . . ,4, are the threshold voltages of the
                                                                                                                 ad    V~~,pi>
this way all “peripheral”                               problems           caused by switching,
                                                                                                                 corresponding    devices. Note that g~ is tunable by adjust-
sample-and-hold                     circuitry,            and       anti-aliasing              and     recon-
                                                                                                                 ing the gate voltages VG1and VG4; USU~lY, ‘G1 = – ‘G4 = ‘G.
struction            circuits       can be avoided.                  Of course, in the analog
                                                                                                                 The       transconductance               parameter         for these composite               de-
 domain,          the designer                 is confronted                with      the serious         and
                                                                                                                  vices is
 challenging             problem              of having           to tune his filter              by some

                                                                                                                                                k?ff      =    ~~k:~),
   Manuscript     received November      9, 1987; revised February      19, 1988.
This work was supported        in part by the Nationaf       Science Foundation
under ,Grant 82-150001.
   Cs >. Park was with the Department
    —.                                       of Electrical Engineering,   Univer-                                 with
citv of Minnesota,
s.., -. . ——..         Minneapolis,    MN 55455. He is now with Intel COrPO-
ration, Santa i Clara, CA 95052.
    R. Schaurx nann is with the Department      of Electrical Engineering,   Uni-
                                                                                                                                           k       = 0.5 peffcox~                         .                   (2)
versity of Minnesota,     Minneapolis,   MN 55455.                                                                                             n,p
    IEEE Log Number       8821663.                                                                                                                      [1                          nip

                                                                            0018-9200/88/0800-0987                  $01.00 01988 IEEE
988                                                                                                                     IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 4, AUGUST 1988

                                                                           v I.         V.ul

               V’fi           &

                       ‘4   18
               vIN            v OU1
                                                u=                                                               Fig.       3.        Inverting      transconductance         element        and smal-signal            model.
                       Vb lb
              VG9             ‘B 4
                      t14      V$$                                                                              ments        1–5 as gti, and assuming                              Ci >> ( CP, CO), the follow-
                                                                                                                ing matrix                 description             can be derived                    from          the circuit,
                      (a)                                                         (b)                           excluding              the output            buffer        consisting        of gm~ and g~~:
Fig.   1.     (a) Simple CMOS linear transconductance    element and circuit
            symbol. (b) Transconductance layout (size: 71X 154 pmz).
                                                                                                                                                                       AV=I                                                  (3)

                                                                                                                             2go + SCl                       gm    –    Scp                                    Scp

                                                                                                                A=                –     Scp            gm + 2go + 3sci                               g. – 2SCP
                                                                                                                             gm –         SC*                gm – 2SCP                   gmQ       + zgO       +     gOQ + “2


                                                                                                                             – gmLvL + sqv~
                            Fig.     2.        g~-C    biquad   building    block.
                                                                                                                I=                              o                                                                           (4b)
The device parameters                           in (2) have their usual meaning                          and
the     equations             are valid                provided        that       all     four      CMOS        V= (VI                    v,         VJ’                                                                    (4C)
devices       are in saturation.                       It is shown in [9] that linearity
and frequency   response can be optimized      by choosing                                                      and where we have defined
proper aspect ratios for the devices; for the parameters of
                                                                                                                                 cl=      Cl+        Ci+2CP+Co+CP~                          +Co~=Cl+Ci                      (5a)
the MOSIS 3-pm bulk                               CMOS process [10] that was used
for the implementation                            of the filter chip, the optimal gate                          and
sizes can be calculated                          to be W/L          = 25 pm/5                  pm for the                                  C2= C2 + Cbuffer +2ci                    + 3C0 +4CP.                             (5b)
p-channel and W/L =20 pm/5         pm                                         for the n-channel
MOSFET’S.  With the transconductances                                          introduced in Fig.               Superscript                t means transpose. Evaluating                               these equations
1, a CMOS             biquad              [11] (Fig. 2) is designed that can realize,                           and neglecting                      insignificant          terms results in
depending             on which                 terminals        are chosen as input,                    high-
pass (HP), low-pass (LP), bandpass (BP) or bandreject                                                                                                                                        Nn(s)
                                                                                                                                               Hn(s)=;                                                                           (6)
(BR) functions.1 For the intended application, four sec-
ond-order BP sections are needed.
                                                                                                                                                                   . ~= O;i#n=                ‘(s)
  At high frequencies, it is unreasonable                                      to expect that the               where n stands for BP, LP, HP, or BR and V~~ = V~ = V~,
biquads        will be of second order;                          rather,      parasitic           elements      i.e., V= and VH are tied together to obtain a bandrejection
will give rise to nondominant                              parasitic       poles and zeros that                 function.              The various            polynomials               in (6) are
may         cause      unacceptable                    performance            at megahertz               fre-
quencies.       To understand                         the behavior,        a realistic           transcon-            D(s)             = 3c1c2Cis3
ductance         model,              as shown in Fig. 3, must be used in the
                                                                                                                                           + [~lczg~          +    3clcigmQ         +    C2cPgm        +    dclc~gm]         L$’2
analysis.        In         Fig.          3,     the     elements          originate             from     the
gate–drain            capacitance                 (CP), the gate–source                        capacitance                                 +    [clgm(gmQ              –   gm )+    zc&mQgij            +      c,gmgO
(C,), and the drain-substrate      capacitance   (CO) of the
MOSFET’S.    In addition,   various coupling     and loading                                                                               ‘2cl%zg0            + clgvzgOQ

capacitances between connection lines should be included,
                                                                                                                                           + cp%&hQ               ‘3cpg;        ]~+g:+gmgo(gmQ–gm)
but to keep the model simple and the analysis tractable,
these and other parasitic components        are neglected be-
cause their effects                       become important    only at frequencies
                                                                                                                 N~P(s)                = Cl(3CiCPs3               –3Cig~s2          – g;s)                                  (7b)
much higher than                          the range of interest. Substituting  the
model        in the circuit                    of Fig. 2, labeling                the identical          ele-    N.,(s)                = g~. (–3CiCPs2+3Cig~s                               +g;)                            (7C)

                                                                                                                 N~P(s)                = C2(3clCis3               + clg~s2         + g%lgos)                                (7d)

  1Unused inputs are grounded. For the BR function,    set V{ = VH = ~n                                          NB~(s)                = 3clC2Cis3 + clCzg~s2
and VB = O. Even an at-pass (delay equalizing)   section can be bmlt:
V~=V~=V~=~.,g~L=g~,g~Q=2gM                                                                                                                 +      fh(c2&70        +WGJ.$                +    %?di.                          (7e)
PARX AND SCHAUMANN: INTEGRATED CMOS TRANSCONDUCTANCE-C BANDPASS FILTER                                                                                                                                              989

                                                                                                                                                                                In            out
For     clarity,      the dominant             ideal    terms        are highlighted          by                                 .-   .------------                          —
                                                                                                                                                                      —- —- — ---------             .
                                                                                                                                                                               ?              7
bold     print.      From       (7a) and (7b),            including         the inverting                                        !
output     buffer       g~e, g~~, the nominal                   bandpass          function—                                      1
the case of most interest                   in this paper—is             given by                                                ,
                                                          c~gms                                                                  !
        HBP(.S) = – ~                                                                        (8)                                 1
                               gin7    C1C2S2+         Cl(&nQ–          %iz)s     + g:
                                                                                                                          ‘ref   1
Note       from       (7)     that     in     N~P(s ) the            second-order           term                                 I
3C1C, g~s 2 can be significant   at high frequencies;   thus,
roll-off on the high-frequency side of the passband will not                                                                     !:::,:,         -----~l::::-----::::---,

be as steep           as on the low-frequency                        side. Similarly,          in
                                                                                                        Fig. 4. Block diagram of fully tuned filter. SF: slave filter; MF: master
N~~(s), the Q factor of the transmission zero, given by the
                                                                                                           filter; PD: peak detector    CG: clock generator;    LF: loop filter; LP:
nonzero term g~(C2 gO+ 3Cig~~), is severely affected by                                                    low-pass filter. A and B are buffer amplifiers/attenuators.    Note that
                                                                                                           the output of the hold circuit~  contains four wires.
parasitic in high-frequency applications. Both these phe-
nomena were actually observed on the experimental   chips
[6] and during              simulation.        Also observe that the S3 terms                           As shown below,                  to reduce internal                     device noise contribu-
indicate       that    high-frequency              signal       feedthrough         must      be        tions,     biquads            with       lower           values        of    UO and              Q should
expected,          as is indeed verified           by experiment            (see Fig. 12).              precede those with higher values in the cascade connection.
   From       (6) or (8), the biquads’                 nominal         pole frequency              is
given by
                                                                                                                                      111.       CONTROL CIRCUITRY

                                        “o=&                                                 (9)
                                                                                                          As discussed in Section II, the filter IC must include
                                                                                                        means that permit the filter to tune itself against errors
which      shows that          tiO tuning        is necessary in principle,                even         caused      by     fabrication                tolerances               and       varying          operating
if parasitic        effects could be neglected,                   because g~ depends                    conditions,  such as temperature. The approach adopted for
on the operating  conditions and because the absolute                                                   this design is a “ master–slave”  system with a conventional
values of both g~ and Ci are subjected to large process                                                 phase-locked             loop (PLL)               for frequency                  tuning         and a four-
tolerances.                                                                                             point     amplitude-locking                    scheme for Q tuning.                         The method
   The pole-quality              factor       Q is ideally           determined          by ele-        will     be explained              with       the help of the block                             diagram     in
ment ratios                                                                                             Fig. 4.

                                Q=        ‘m                :                                           A. VCO Design
                                        gmQ– gm                  1
                                                                                                           All    VCO’S in the control                          loops are biquads,                      identical   in
                                                                                                        layout     and design to the one shown in Fig. 2, except that
but evidently,          from (7a), parasitics-in                     particular     gO—will
                                                                                                        signal     input, VB = V~ = VH, is ground (no g~~) and the Q
have a strong effect on the actual value of Q; this is the
                                                                                                        factor      is set to infinity. For a well-defined process, the
case especially for large Q, i.e., small values of gmQ – gm,
                                                                                                        Q-control        voltage           can be generated                     internally              ( = – 3.5 V
and at high frequencies                     where the size of parasitic                  capaci-
                                                                                                        at 5-V power supply). For a wide-tolerance     process, how-
tances is of the same order as the circuit                            capacitors.2 If the
                                                                                                        ever, this control voltage should be accessible to avoid the
realized passband shape and bandwidth                                  are to be correct
                                                                                                        possibility  of shifting the VCO                                    frequency       when poles are
in high-frequency     applications, it should be apparent,
                                                                                                        too far in the right half plane.3
therefore, that Q tuning will be unavoidable, even if some of
the effects may be eliminated through predistortion       after
                                                                                                        B. The Frequency-Control                            Loop
careful modeling.
   A final factor to be observed is the finite range of linear
                                                                                                           The frequency-control                         loop implemented                     on the chip is
operation          of the active transconductances.                       Thus, for opti-
                                                                                                        a conventional                PLL        with         an infinite            Q-factor            biquad     as
mum dynamic             range, the signal level of the biquads                            has to
                                                                                                        ~-VCO,       an          RC          filter        as        loop       filter      (LF),           and     an
be scaled appropriately                  [12], [13] which is accomplished                     by
                                                                                                        EXCLUSIVE-OR                 (XOR)       gate as phase detector.                            The j-VCO
the buffer         amplifiers         consisting       of g~c and g~~.
                                                                                                        biquad      oscillates          at a frequency                      given by (9) which                differs
   With    these guidelines  in mind,      the eighth-order
                                                                                                        from the filter pole frequencies by at most a designable
Chebyshev bandpass filter is constructed by cascading four
                                                                                                        constant (a capacitor   ratio). The VCO frequency error,
BP sections with nominal     pole frequencies  and Q fac-
tors (fp, /MHz,   Qi,. i=~,. . . ,4) of values 3.5807/23.9,
3.8090/9.83,           4.1586/9.83,             and 4.4237/23.9,                respectively.
                                                                                                           3Note from (7a) that for infinite                            Q the pole frequency     is slightly
                                                                                                        reduced ( g~ = gm !). To compensate                             for this effect, by (9) the capaci-
                                                                                                        tances of VCOS %ould be designed                                slightly smaller than the nominal
  2A1s0 the source impedance                can have an effect on Q! (see (16)).                        values of the biquads.
990                                                                                                                         IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 4, AUGUST 1988

                                                                                 &                                  ode at the MOSFET                            of the multiplexing                     switch         can be
                     0                                                           ~         0.5    d.
                                                                                                                    significant         when       the junction                  temperature            is high. In that
                                                                                                                    case,     external           hold         capacitors            may         be necessary.5               The
             3     -5                                                                                               clock     circuitry       generates               four-phase           nonoverlapping                 clock
                         : ~pi
             .;                                 3 82MHz       4 14MHZ                                               signals. As discussed in [6], the Q-VCO                                      output       signals (Fig.
             o                                     T-2           r3
                                                                                                                    5) are fed into           the master filter                    one at a time under clock
                                    3 63 MHz                            4 37 MHZ                                    control       and      the amplitude                    response            of the filter           at the
                                      fl                                  f4
                                                                                                                    Q-VCO     frequencies, which are nominally    the reflection
                                                                                                                    zeros, is compared to a reference voltage that is generated
                         34         36          38       40      42        44         46                            from      the Q-VCOS.
                                                Frequency      (MHz)
                                                                                                                       Because          by    (8)        the midband                  gain        of    the     biquads        is
              Fig.       5.    Filter     passband       and Q-control         frequencies                          proportional           to a designable                       g~ ratio        and to Q, one may
                                                                                                                    conclude        that         any      measured                gain     error        at the         Q-VCO
                                                                                                                    frequencies          can be attributed                         to a Q error               and can be
when       compared              to ~,ef, results              at the LF             output            in a dc      corrected by tuning Q. Further, the heights of the pass-
error signal that is applied in an appropriate                                        manner            to the      band ripple peaks of the cascade circuit (see Fig. 5) can be
g~ gates ( ‘G1,4 ‘f gml- 5 ‘n ‘ig. l(a)) ‘0 ch~ge  gm and                                                           shown to be dominantly       determined  by the section Q
thereby tune the ~-VCO oscillation      frequency until the                                                         values which in turn are affected by parasitic, in addition
error is zero. The required loop gain is attained from the                                                          to source and load conditions                                 as pointed           out earlier.          The
XOR gate. The time constant of the RC loop filter affects                                                           adopted       procedure              is, therefore,             a complete           functional          tun-
the tuning         range of the PLL and was designed to be 0.5 ps.                                                  ing scheme            that     corrects               the Q errors              regardless         of their
Additional            RC filtering                   (LP) with         much larger               time con-          origin,     because           the biquad                sections       work         in their       natural
stant is used for cleaning                            the bias signal from                  the remain-             environment,             the full           eighth-order              filter,      and master            and
ing      high-frequency                   noise        and      other      interference                 before      slave are identical                  in all details.             The errors           are processed
entering      the filter            blocks, including                  the master/slave                 filters     and fed back             to the gate control                         terminals,           ~Gl,4,    of   the
and the Q-VCO’S                      for the Q-control                   loop. Attention                 must       transconductances                    gmQ         in    the     corresponding               master        and
be paid to designing                       the transition              voltage of the XOR gate                      slave     biquads        to    set       their        Q factors        [6]. The Q-VCO’S                  can
to match           the center               of the analog                VCO         output            signal.4     consist of either one biquad and a capacitor array with
Sections 1–4 of the Q-VCO’S and of the master and slave                                                             switches, or of separate biquads matched to the corre-
filters are matched  to the ~-VCO;  therefore, the error                                                            sponding        filter        sections.           The former                scheme is found              not
correction         signal generated by the ~-VCO,                                when applied                  to   practical      for high-frequency                        applications              because of para-
the remaining                 12 biquads,              will correctly          tune all frequency                   sitic     switch      capacitances                    [6]. In        this    paper,        the      second
parameters               throughout                  the chip.         Experience            has shown              method        was used. The                      amplitudes             of the VCO                 outputs
and it can be verified from (7) that pole frequencies, in                                                           depend        on frequency                 and cannot                be adjusted            exactly      be-
contrast to pole-Q factors, are not very sensitive to para-                                                         cause only one Q-control                          voltage is applied                to all VCO’S of
sitic;      matching            does not, therefore,                     appear to be a prob-                       different  oscillation frequencies. For applications at lower
lem.                                                                                                                frequencies, the VCO output can be easily amplified to the
                                                                                                                    maximum      swing (square wave) that the transconductance
C. The Q-Control                    Loop                                                                            can handle (2.5 V at 5-V power supply) and attenuated by
                                                                                                                    either a resistive voltage divider or simply by resistive
   The      Q-control               loop consists              of Q-VCO’S,             master            filter,
                                                                                                                    loading;       therefore,             the spectrum                of VCO             output         signals
peak       detector,           comparator,                  holding      circuitry,              and     time-
                                                                                                                    can     be set to be uniform                             in    magnitude             and       thus      one
sharing       clock           generators              [6]. The master            and slave filters
                                                                                                                    reference       voltage            for      the peak            detector           is sufficient.         Of
are identical.                The        four        Q-VCOS        generate          frequencies               at
                                                                                                                    course,     higher       harmonics                    are thereby           added to the signal,
the      reflection           zeros        of the filter,              i.e., points              of perfect
                                                                                                                    but here the discussion                          is confined to the case of filters
transmission,   as illustrated in Figs. 5 and 12. The peak
                                                                                                                    with reasonably  narrow                          passband where these harmonics
detector consists of a diode (a low-~ n-p-n transistor with
                                                                                                                    can be filtered out in the master filter. For high-frequency
collector connected to V DD; ‘n low-frequency   applications,                                                       applications,  the reference signal should be generated by
the diode can be replaced by precision diode), a 10-pF
hold capacitor,   and a discharging resistor. The Q-control
signals are stored on the hold capacitors in Fig. 4 which
should sustain the voltages until the next update period.                                                               ‘In any junction-isolated     process the leakage currents will be at least of
                                                                                                                    the order of 1 pA and possibly much higher for hrgh junction               tempera-
Note, though, that leakage through the reverse-biased di-                                                           tures. Thus, with on-chip hold capacitors            limited   to a few picofarad,
                                                                                                                    storage tlmes~ before drooping occurs, will be measured only in seconds
                                                                                                                    or even fractions      of seconds. Externaf hold capacitors will, therefore, be
   41f the transition voltage is larger than the magnitude     of the VCO                                           difficult  to avoid unless very frequent charge updating can be employed.
output, the XOR gate will never switch and the phase comparison        breaks                                       As described in SectIon VI, external hold capacitors were used for our
down. In situations where unmatched VLSI library components         are to be                                       circLut; with these, the Q-control         loop functioned      correctly for clock
used for convenience   (as done in the present design), the problem can be                                          frequencies    (externally    controllable   for testing purposes) in the range
avoided by amplifying    the VCO output to assure sufficient    signaf swing                                        1 Hz< ~ <100 kfi.           Any clock feedthrough      is thereby well outside the
to drive the XOR logic gate.                                                                                        passband.


          E                                                                                                                                    -i
                                                                                                                                               o   .                              9 on


                    v GI                                                                                                                                                             I
                                              v G1                                                                                                                                                        1nnl
                                                                                                                                                                  y?                                     T
                                                                                                                                                      (a)          ‘n
                                                                                                                                       *                                          9 0n3
                                              .                                                                                                                                                          T
                                                                                                                                           9                       4?                                     1nn3

                                                                                                                                                             go                  9 Opa                   T
                    v G4                      VG4                                                                                                                                                         1npd
                  (a)                 (b)                    (c)                  (d)                                                                                                              (c)

                  Fig.     6.    (a)–(d)     Different       bias generation     circuits.                                                  Fig.      7.      (a)–(c)     Noise circuit        models.

an additional               matched peak detector from the VCO out-                                           a factor       2 of the nominal                            center         frequency                for frequency
puts directly               as shown in Fig. 4. The transfer functions                                        control and unlimited   for Q control (unless parasitic out-
of both paths (see Fig. 4), VCO – attenuator A – master                                                       put conductance     gO become comparable to the transcon-
filter - peak detector and VCO - A – peak detector-  B,                                                       ductances  g~                        as may               be    the           case     for         short-channel
should,       of course, be matched.                           A digital        circuit      version     of   MOSFET’S).
this Q-control                  scheme can be found                       in [15].
                                                                                                              E. Offset-Zeroing                       Loop
D. Bias Generator                      Design
                                                                                                                   Although           not           part       of the intrinsic                    tuning         loops,       offset
   As pointed                   out before,           the control            loops generate            bias   zeroing       is nevertheless                        an important                aspect of the overall
signals which must be applied to the gates of the ap-                                                         control      scheme: if dc offset voltages become too large, not
propriate transconductances. Consequently,    design of the                                                   only will the filters suffer from reduced dynamic range and
bias generator   (BG) is very important    for the overall                                                    increased   distortion,   but more importantly,   the tuning
performance                of the filter,             including           the tuning         loops.    BG     loops      will        not           function             correctly            because             the generated
generates           two bias voltages,                   V~l and l(~d in Fig. 1, which                        bias voltages                will       lose their required                      symmetry                to ground.
for most cases [9] satisfy                                                                                    To       assure         negligible                  dc offset,            the        design          includes           an
                                                                                                              automatic               offset-zeroing                     loop,          consisting                of     reference
                            vG1=–vG4=vG=vGo–f(~).                                                     (11)    transconductances                        that are matched                       to the filter              transcon-
                                                                                                              ductances. The dc offset of the reference devices is “com-
In (11), VC is the bias control voltage generated by the
                                                                                                              pared to ground” and the appropriately   amplified dc error
frequency- and Q-control  loops, and ~( VC) is not neces-
                                                                                                              signal is applied to the backgates ( VB1) of the devices Ml
sarily       a linear function (apart from some special applica-
                                                                                                              in Fig. 1 of all circuit transconductances      to reduce dc
tions,       such as analog multipliers).  For the MOSIS bulk
                                                                                                              offset     to zero. Implementation                                 details           can be found                in [9]
CMOS          case with               +5-V         power           supply,    feasible       ranges are
                                                                                                              and [15]; it can be shown that V~l is always in the rimge
3.5 V < VG<5                     V and            –1.5   V<          VC<1.5      V. Fig. 6 shows
                                                                                                              Vb < VBI <  V. (see Fig. l(a)). In the experimental circuit in
various       bias generation                     circuits     [15]. Each of the circuits                in
                                                                                                              this     paper,         dc offset                was kept             at less than 4 mV for all
Fig.      6(a)–(d)              has its advantages                    and disadvantages:                for
                                                                                                              transconductances                        throughout               the chip.
example,           in circuit               (a), V~ is process independent                        and a
linear       function            of    ~;     circuit        (b) has high PSR; circuit                  (c)
lends itself to designing                         a temperature-independent                     biasing                         IV.            NOISE          AND        ORDERING              OF BIQUADS
scheme; and circuit (d) permits wide device tolerances. On
the other hand, circuits (a), (c), and (d) have poor PSR and                                                       Low-frequency                       noise            sources        of MOSFET’S                       and     also
circuits      (a) and (b) need one VT between power supply and                                                high-frequency                       gate-induced                noise          are not            significant          at
the maximum                     value of F&.                                                                  the operating  frequency of the filter. Therefore,  thermal
   For       the complete                    tuning      operation            of the eighth-order             noise from the devices themselves is the major noise source.
filter,      13 biquads                are needed:                 four    each for       master       and    A noise equivalent                            circuit      for a transconductance                            element
slave filters,             and for the Q-control                       VCO’S, and one for the                 and noise characteristics                                 of the biquad                from         its transcon-
~-VCO.            The biquads                 for the master                 and slave filters          are   ductance           elements                  can be easily derived                         as follows.
identical;  those for the VCO’S differ slightly from those of
the filters to account for the frequency shift caused by                                                      A. Noise Equivalent                            Circuit         of the Transconductance
Q-factor differences (infinite Q for the VCO’S).3                                                             Element           [14],          [17]
   As shown in Fig. 2, eight inverting     transconductance
                                                                                                                   A    noise-source                  representation                  of     an individual               transistor
elements are required to build a completely tunable band-
                                                                                                              is shown          in    Fig. 7(a), with
pass biquad. Reasonable tuning ranges, without affecting
linearity          and dynamic                    range severely,              are, of course,          de-
termined by the type of transconductance      circuit chosen;
for the devices in this paper, Fig. 1, the ranges are around                                                  where        K = 2/3,                 assuming              hot-electron               noise         and     induced
992                                                                                                                                                       IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 4, AUGUST 1988

gate      noise             are      a      small                  fraction             of         thermal             noise.          Also       with
low-frequency                      noise         is not               included                because             it    is insignifi-
cant    at frequencies                      above                  100    kHz.          With         (12),        the       MOSFET                                 N(s)         = –      scl(g,u~        +~)+(scl+                       g,)~

noise         circuit          shown             in          Fig.        7(b)         and          the     simplified                 noise
sources          in
                        Fig.        7(c)
                                                                      derived;                it
                                                                                                    is assumed                 that
                                                                                                                                           the                                      ‘[SC+-5+4-
                                                             all    p-channel
                                                                                             identical.            With
                                                                                                                             and      of    all

                                                                                                                                                                                    ++==%   —
                                                                                                                                       (13)                                     —
                                                                                                                                                                                - ‘sclg2(u’2+lti:.)
                                                                      go.       + gop

                                                               g~pi~n         +       g~.i~p
                                           ;;=2                                                                                        (14)
                                                                      g:. + 82P

Fig. 7(b) is also an approximate                                                   equivalent                noise model of
the     complete                    transconductance.                                    Noise               from            the       bias
sources, VG1and VGd,can be considered                                                                by adding                g~~lii~~l
                                                                                                                                                  is     the       equivalent             input     noise         obtained             by reflecting             all
to ;~fil and g~Pd6~~b to ;~pz, where ti~~l and ~~~e are noise
                                                                                                                                                  noise sources                  to the biquad                input.          Note      that the transfer
voltages          for the bias generators                                         F’& and VG4, respectively.
                                                                                                                                                  function               for    the noise contributions                          to the output                has a
Noise coupling                      through                   power supply lines is not discussed
                                                                                                                                                  low-pass               rather      than         a bandpass                  characteristic.           For      the
here, because noise coupling                                                through                 parasitic               capacitors
                                                                                                                                                  devices used in the experimental                                      circuit,       the noise sources
depends           on unknown                          factors of layout                             and processing                         and
                                                                                                                                                  can be calculated to be ~~~1 j~~~ = 3.47,10 – 25A2/Hz,                                                        and
the transconductances themselves have high power                                                                                   supply
                                                                                                                                                  i;p2 = ;;P4 = 2.86.10 ’25 A2/Hz; with these numbers                                                           and
rejection ( >90 dB up to ~ = I MHz) [9].
                                                                                                                                                  the          same            assumptions              as       above            and      Cl = C2,              the
                                                                                                                                                  equivalent               input     noise in midband,                        up = g~/@,                      of the
B. Inherent                 Noise of the Biquad Building                                                 Block
                                                                                                                                                  biquad           is 26.5 nV/@.                        For a signal amplitude                          of 0.5 V
  Applying  the equivalent circuit                                                       shown            Fig. 7(b) to the                        and 800-kHz      bandwidth,   the intrinsic   signal-to-thermal
bandpass biquad shown in IFig.                                                          2,     but        without               gmL,6,T,          noise ratio is, therefore, approximately    80 dB.
nodal         analysis             results            in           A V=       1 with                                                                   As      shown            by (16),          at the output,                   the internal           device
                                                                                                                                                  noise for a bandpass                        biquad           has a low-pass                 characteristic
          /g,         + Scl                  – Scl                                o                                     0                         proportional                  to Q, i.e., the lower                     stopband         is more noisy
                        Scl              80+ Scl                                gm                                      o                         than the upper stopband and the high-Q biquad has higher
 A=              –0                                                                                                                               noise. Therefore, to reduce passband noise, lower center
                                                     0                   ~m +Zgo                                       g.
                                                                                                                                                  frequency               and lower Q biquads                      should precede those with
                        o                        8.                             g.                   “2       +        gmQ     +   3&J
          \                                                                                                                                       higher           center       frequency           and higher                 Q factor         to minimize
                                                                                                                                    (15a)         internal          device noise contributions.                               Note, however,            that for
                                                                                                                                                  a filter  with fully operational  automatic tuning,    signal
 V=(VB                  VI         V2           ~)’                                                                                 (15b)
                                                                                                                                                  feedthrough   from VCO’S, digital parts, master filter, and
                                                                                                                                                  control           loops         will     generally           be a more                serious         problem
                                                                                                                                                  than inherent                 device noise.

 I=                                                                                                                                 (15C)
                                                                                                                                                                                    V.      TEMPERATURE DRIFT

          \@-==                                                                                                                                        From         (7)–(10)             it is apparent                that     temperature-induced
                                                                                                                                                  changes           of     frequency          and       Q     factor          depend     directly        on     the
where          u,, is the input                              voltage              source,             connected                    to the         term         dg~/a           T and, by (7a), also on                           i3( g~/gO)/a            T. The
bandpass input VB                               in Fig. 2, and g, its output conduc-                                                              change of transconductance                                   with           temperature           T    can     be
tance; i;, is thermal                            noise current of g~. An approximate                                                              calculated from (1) as
solution,          neglecting                   nondominant                             terms with                     go << gm <<
                                                                                                                                                                    agm            gm                                                     a XVT
8,2is                                                                                                                                                                              —— akeff         +    Ak        a J%
                                                                                                                                                                                                                   —            –2k,~~—                        (17)
                                                                                                                                                                    aT = ke~~ i3T                              ‘ff a T                        aT

   ‘=gs{s2clc2+scl[J:::~~(l-:)l+g:}                                                                                                               where        a   (XV~)/il
                                                                                                                                                  – 0.005 k .~~(qw~)/OC
                                                                                                                                                                                     T = –8 to –10
                                                                                                                                                                                               around           room
                                                                                                                                                                                                                       mV/°C           and ake~~/aT=
                                                                                                                                                                                                                               temperature.             For     the
PARK AND SCHAUMANN: INTEGRATED CMOS TRANSCONDUCTANCE-C BANDPASS FILTER                                                                                                                                                       993

                                                                Fixed      bias      ( 4.5V)
                     ~        ,“,                                                                                                                                     vrc=~–vc.
                     mu                                       R =30k       Q, TC=0
                                                                                                                                The     temperature            coefficient      for diffused          Si resistors          is a

                                                                                                                                few hundred           to a few thousand              ppm and that for metal-film
                     ~E -1o-            R =37.5ks2                                                                              resistors        can be as low as a few tens ppm.                            Substituting
                                                                                                                                (20a) into (19) yields
                              -2” ~
                                    o          20              40           60            80          I 00
                                                         Temperature          (“C)

Fig.    8.     Simulated            transconductance                 change with temperature                       for tem-
                                    perature-tolerant               biasing scheme.
                                                                                                                                which      by comparison             with (18) results in

transconductartce                         element,                  the      temperature                     coefficient                              kef~(~c–0.5W~)~                   b=0.5
equals         dg~       /a    T = – 0.4 pS/°C                        and that of the internal
voltage         gain,           g~/gO,              is        d (gw/gO)/~  T = – 0.06/°C, as-                                                                                 ib;           =0.25~
suming ilVG/8T = O [16].                                                                                                                                                              eff              eff
  As discussed in Section                                     II, component                     drifts       caused by          and, with         (1) and (20a)
temperature               variations                during            operation                are eliminated              or
reduced          by the control                      loops. Nevertheless,                             the operating                                    VG= Ibl?b +0.5X’~
and tuning range of the filter can be increased if device
                                                                                                                                                       ~,=      21bkb +0.5H’~                = VG+ Ibiib
parameter changes are intrinsically compensated. Although
not      included              in        the    experimental                         chip,       an appropriate                                     VDD/= VG+ IbRb.
scheme for accomplishing                                      such compensation                          is presented
in the following.                                                                                                               If the bias generator                supply    voltage        V:D ( = VDD) and g~
       Most      dc device                parameters                      of MOSFET’S                    change lin-            are given, VG and V,C are determined in the above equa-
early        or nearly              linearly         with           temperature.                 Threshold            volt-     tions, assuming 2Y’~ and R\ – Rb are constant. From (la),
age changes                   as – 2 to                   – 2.5 mV/°C                          according           to the       VG, 2YT, and ~c are calculated; also Ib is determined by
changes          of bandgap,                    intrinsic                 carrier         density,           and junc-          (20a) so that   Rb can be computed from the above equa-
tion         potential.              The       transconductance                                element,           k = 0.5       tions. In practice,  12VT (including back-gate effects) de-
                                                                                                                                pends on VG and VDD, and R~ – Rb depends on Ib, among
PCoxW/L,  varies as T – 15 because of mobility  changes.
Around room temperature,   k changes by 0.5 percent/°C                                                                          other factors. Therefore, an approximate  sOhftiOn, R b, can
[16].                                                                                                                           easily be found and can be further    refined by a few
                                                                                                                                simulations. Some SPICE results for the values and pro-
A. Temperature-Insensitive                                     Transconductance                       Bias Design               cess parameters             on the experimental               chip are shown in Fig.
                                                                                                                                8. They         indicate      that the above relations                can be satisfied
       From       (17),             g~     will          be independent                          of      temperature            with reasonable              values of R b and for different                 temperature
( 6’g~/d        T = O) if the temperature                                         derivative             of the bias            coefficients.         The     predicted        transconductartce             drift     is less
voltage         V~ satisfies                                                                                                    than 3 percent              over the temperature              range from O to 70° C
                                                                                                                                (for a fixed bias, it is 22 percent).
                          a VG                      6’XvT

                         37=0”’                     7“0”2’2%”                                                          (18)

                                                                                                                                          VI.       EXPERIMENTAL RESULTS AND DISCUSSION
One example of a suitable bias circuit is shown in Fig. 6(c),
                                                                                                                                   Fig.     9 shows          a photograph             of the filter         chip     with    all
with VG1 – VGA.From Fig. 6(c), assuming RI= R ~= Rb
                                                                                                                                control         circuitry      and     some         additional       test    circuits       not
and that all n-channel                              and p-channel                       FET’s,           respectively,
                                                                                                                                discussed         in this paper. The filter                  system functioned              cor-
are identical,                it follows            that
                                                                                                                                rectly, but a few minor external components                                   were neees-
                                                                                                                                sary: in the frequency-control  loop, a load                                 resistor was
                     8 VG                                             r?Rb
                     —=–                   Rb:–                     Ib—    = – iib;                                    (19)     connected          to the ~-VCO          output        to shift its dc level to the
                     aT                                                8T                                                       transition        voltage      of the following             MOSIS-library          XOR gate
                                                                                                                                (see footnote 4 for methods to avoid this resistor). Once
where                                                                                                                           the ~-VCO was locked to the external reference frequency,
                                                                                                                                no frequency    error between ~-VCO, the filter,                                    and the
                                                                                                                                reference signal was noticeable on a spectrum                                      analyzer.
                                                                                                                                For     the reference           frequency           (design      value)      of 2.9 MHz
                              (aRb/aT)                                                                                          (away,      but “not too far” [4], from the passband), the filter
  iib=Rb+                                                                                                            (20b)
                              ( aIb/aT)                  Ib                                                                     center      frequency  was 4 MHz as desired. No significant
994                                                                                               IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 4, AUGUST 1988

                                                                                                             Fig.    11.       Tuned    and untuned   filter    performance,

Fig. 9. Photograph    of the CMOS filter chip. Totaf area 6900X 3400
   pm; areas for the slave filter, master filter, and Q-control oscillators:
   560 x 1100 ~m each.

                                                                                           Fig.    12.     Overall    filter    performance     and, on lower        trace, noise,    Q-, and
                                                                                                                                frequency-control    signals.

                                                                                           Furthermore,              on the designed chip the capacitor                         nodes are
                                                                                           connected            to    pads        for     testing     purposes         where      reverse-
                                                                                           biased junctions                 for input         protection       add additional          para-
                                                                                           sitic diodes. On the chip7 the Q-control  comparator was
                                                                                           designed with transconductances   (Fig. 1) for a nominal
                                                                                           gain of value three for stability of the loop. The actual gain
                                                                                           was less than two because of a processing error in the bias
Fig.   10.    Passband   detail    of the filter performance     at O“C (lower    trace)
                                       and at 65°C.
                                                                                           circuitry which, together with a limited dc swing ( < +2.5
                                                                                           V),     resulted          in a narrower              Q-tuning        range than        desired.
                                                                                           Although           the experimental                performance          was quite reason-
frequency        drift    over      the commercial             temperature       range
                                                                                           able,         evidently         from        Fig.    10, the         Q-control       range    was
could        be observed (Fig. 10). In the experiment, the auto-
                                                                                           insufficient         to maintain              the exact passband            shape over the
matic        frequency-tuning  range was from 3.3 to 4.3 MHz
                                                                                           full design temperature                      range.G
and that for Q tuning was around 40 percent of its
                                                                                              Fig. 11 shows the filter characteristics in the vicinity of
nominal    value. (With manual control, by overriding       the
                                                                                           the passband at room temperature with both control loops
control  loops, the corresponding    ranges were 2.6 to 4.3
                                                                                           closed and, for comparison,   with both loops open (inac-
MHz for ~ tuning and unlimited       for Q tuning, i.e., from
                                                                                           tive). Note that the frequency parameters for the uncon-
very wide bandwidth    (low Q) until oscillation.)
                                                                                           trolled case are close to the design values, but that the
   For the Q-control loop, charge leakage from the on-chip
                                                                                           quality  factors, being very sensitive to parasitic,                                        show
hold capacitors          (40 pF each) of the Q-control                voltages was
                                                                                           large errors. Finally, Fig. 12 shows the overall filter                                   perfor-
observed        to be too large so that external                  capacitors     were
                                                                                           mance between                   O and 20 MHz             and, as reference,          a second
connected        to avoid         drooping.5     This leakage is caused by
the reverse-biased    diodes where the leakage current in-
creases exponentially     with temperature  (a problem that
                                                                                              6The main reason for this finding is the incorrect                      value of the p-well
gets more severe at high frequencies) and also depends on                                  resistors RI and R ~ in the bias circuit of Fig. 6(c):                     the measured sheet
                                                                                           resistance  was found to be only one-third      of the                     published   nominaf
bias. One reverse-biased diode at the source or drain of a
                                                                                           MOSIS specification   which prevented the gate-tuning                      voltages from span-
switch (Fig. 4) is unavoidable     in the proposed scheme.                                 ning the full design range.
PARX AND SCHAUMANN: INTEGRATED CMOS TRANSCONDUCTANCE-C BANDPASS FILTER                                                                                                                                                995

                                       TABLE I                                                                            mental         chip,    signal     interference      among       master/slave         filters
                               EXPERIMENTAL FILTER DATA7
                                                                                                                          and      VCO’S          through       the frequency-control               lines was ob-
                                                                                                                          served7; to reduce this problem,                      external         grounded      capaci-
                Control                                         Automatic           Manual
                                                                                                                          tors      were         used      to reduce        feedthrough.          Signal     or noise

                Passband      ripple                                   1 dB          O 5dB
                Stopband      attenuation                                 >60dB                                           interference            through       power       lines is negligible            because of
                Bandwidth                                        800     kHz
                                                                                                                          the high          PSRR           of the transconductances.                In     the layout
                S/N    In passband                              z40dB                75dB
                D1stortlon      (for 05 Vpp)                     o 5x                                                     shown        in Fig. l(b),           a transconductance            is designed         like a
                max signal        level                           I 2vpp                                                  polycell;   therefore, chip layout design was more like that
                Frequency      control        range               I MHz             I 5 MHz
                Q-cantrol      range                              40.%              unlimited
                                                                                                                          of a digital IC. Also in the layout, possible latch-up occurs
                Offset    (reference     lnverter)               lmv     I?    Galns50                                    only between M2 and M3; it can be easily suppressed by a
                                                                                                                          vertical ~~~ diffusion   line as shown. Also this diffusion
                                                                                                                          line works to isolate possible high-frequency interference.
trace     (obtained            by grounding                     the filter               input)          with      the’          Experimental           results for an additional                1O-MHZ filter        on
system       noise         floor,        the four           multiplexed                    Q-control              fre-    the chip indicated                that the methods          adopted       can work also
quencies           (compare               with          Fig.           5),      and         the          2.9-MHz          at higher frequencies                if appropriate         care is taken. However,
frequency-control                    signal. Note               that as predicted                        the high-        at      even      higher         frequencies,      signal    interference          between
frequency             transition            band         is less steep                    than           the     low-     master         and slave filters           and the tuning          blocks        becomes a
frequency          one and high-frequency                                attenuation                  is reduced          problem           that requires         careful     attention      to layout         and de-
due to parasitic  feedthrough.    Some additional    measured                                                             sign.
performance   characteristics  of the filter are contained in
Table      I. Some dependence of center frequency on the Q                                                                                                   ACKNOWLEDGMENT
factor     was observed because the parasitic output conduc-
tance      of     the      MOSFET’S                   was larger                than        expected              (see         Processing          of the final        chips by the MOS              Implementa-
(7a)); therefore,             the relative position                      of the center frequency                          tion     Service (MOSIS),               Marina       Del Rey, CA, is gratefully
of each biquad               was not exact to filter                             specifications.                 This     acknowledged.
problem         may         be unavoidable                  at high              frequencies                   due to
the wide process tolerances                             necessitated               by using different
   Because of the several functional                                    blocks on the test chip,                           [1]     J. O. Voorman         et al., “Integration      of analog filters in a bipolar
                                                                                                                                   process,”    IEEE J. Solid-State         Circuits, vol. SC-17, pp. 713-722,
unrelated to the filter system, accurate measured data of                                                                          Aug. 1982.
power consumption      are not available; but approximately                                                                [2]     Y. ~sividis, M. Banu, and J. Khoury, ” Continuous-time             MOSFET-C
                                                                                                                                   filters in VLSI,”        IEEE J. Solid-State        Circuits,  vol. SC-18, pp.
900-mW    power consumption      can be estimated    for the                                                                       15–30. Feb. 1986.
overall      blocks         (frequency-,                Q-, offset-control                       loops,         three      [3]     H. Khorrarnabadi          and P. R. Gray, “High-frequency          CMOS con-
                                                                                                                                   tinuous-time    filters;     IEEE J. Solid-State Circuits, vol. SC-21,pp.
eighth-order              filters,       and clock               generation)                    of     this     filter             939-948, Feb. 1984.
( <200       mW for one filter                        circuit      itself).                                                [4]     C.-F. Chiou and R. Schaumann,                 “Design     and performance         of a
                                                                                                                                   fully integrated       bipolar 1O.7-MHZ analog bandpass filterfl           IEEE J.
                                                                                                                                   Solid-State     Circuits, vol. SC-21, pp. 6-14, Feb. 1986.
                                                                                                                           [5]     K. Miura       et al., “VCR        signaf processing LSIS with self-adjusted
                                       VII.           CONCLUSION                                                                   integrated     filters,”    in Proc. Bipolar Circ. Tech. Meeting ( f3TCM),
                                                                                                                                   Sept. 1986, pp. 85-86.
   The paper shows that CMOS                                    transconductance-C                             filters     [6]     C. S. Park and R. Schaumann,                “Design     of an eighth-order       fully
                                                                                                                                   integrated     CMOS 4MHz continuous-time               bandpass filter with dig-
can be practically                   useful           at video          frequencies,                  with      large              ital/analog       control of frequency and quality factor,” in Proc. Int.
                                                                                                                                   Symp. CAS, May 1987, pp. 754-757.
S/N    ratio            and wide dynamic         range. The                                             proposed           [7]     R. Schaumann             and C.-F. Chiou, “Design          of integrated     analog
frequency-,            Q-factor, and offset-control   circuitry                                          operated                  filters, “ in Proc. 1981 European Conf. Circuit Theory and Design
                                                                                                                                   (ECCTD)        (The Hague, The Netherlands),            Aug. 1981, pp. 407-411.
correctly.         Some         minor            problems               and       possible               solutions
                                                                                                                           [8]     D. Senderowicz,           D. A. Hodges, aud P. R. Gray, “An NMOS
were pointed               out in the text. Extreme                               attention               must be                  integrated     vector-locked       loop, “ in Proc. IEEE Int. Symp. CAS,
                                                                                                                                   1982, pp. 1164-1167.
paid      to possible             coupling              of internal                 ~- and               Q-tuning
                                                                                                                           [9]     C. S. Park and R. Schaumann,                “A high-frequency        CMOS linear
signals      as well        as clock             signals into                 the main               filter;    thus,              transconductance           element.” IEEE Trans. Circuits Svst.. vol. CAS-
                                                                                                                                   33, pp. 1132-1138,           Nov. 1986.
very careful           design and layout                   are necessary. In the experi-                                  [10]     MOSIS — Users’ Manual, Inform. Sci. Inst., Univ. Southern Calif.,
                                                                                                                                   Los Angeles.
                                                                                                                          [11]     C. S. Park and R. Schaumann, “Fully                 integrated   analog filters in
    7For manurd control,          the Q-control    oscillators   are OFF so that the                                               CMOS        technology,”       in Proc. Int. Symp. CA S, May 1986, pp.
signal-to- thermal     noise ratio is = 75 dB (see Fig. 12). For automatic                                                         1161-1164.
control,   the Q-control       loop is ON and the four multiplexed            Q-control                                   [12]     K. R. Laker, R. Schaumann,                and M. S. Ghausi: “Muftiple            loop
signats are found to couple into the slave filter, reducing the signal-to-                                                         feedback topologies for the design of low sensitivity                active filters;
‘<noise” ratio to = 40 dB. Experimentally,               the f eedthrough    paths were                                            IEEE Trans. Circuits Syst., vol. CAS-21$pp. 1–21, Jan. 1979.
determined     to be the gate-control       bias lines. On the designed chip, the                                         [13] C.-F. Chiou and R. Schaumann,“A refined procedurefor optimiz-
gate control lines are the same, i.e., direct connections for simplicity,             for                                      ing signat-to-noise ratio in cascadedactive RC filters,” Proc. Inst.
the Q-control       oscillators,    master and slave circuits        without    any HF                                             Elec.    Eng., vol. 128, part G, Electron.         Circuits    Syst., pp. 189-191,
isolation   or additional       low-pass filtering   as adopted for the frequency                                              Aug. 1981.
 control loop (see Fig. 4). It is not hard to show that a further simple                                                  [14] A. Van der Ziel and K. Amberiadis, “Noise in VLSI,” in VLSI
 low-pass filtering    in the bias lines before they enter the slave filter or,                                                    Electronics, vol. 7. New York:             Academic, 1983.
 better, using separate bias circuitry can reduce the four Q-control spectral                                             [15]     C. S. Park. “A CMOS linear                 transconductance       element    and   its
 lines m Fig. 12 by more than 30 dB so that an S/N ratio of the order of                                                           applications in integrated high-frequency filters,” Ph.D. disserta-
  > 70 dB can be achieved.                                                                                                         tion, Univ. of Minnesota, Minneapolis, Dec. 1987.
996                                                                                        IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 4, AUGUST 1988

[16]   C. M. Botchek,   VLSI— Basic MO.S Engineering,             vol. 1, Pacific                                Rolf Schaumann (S’70-M79-F’86)             received the
       Technicaf Group, Inc., Publications Div., Saratoga,        CA, 1983.                                      Diplom-Ingenieur       degree from the University     of
[17]   S. K. Kim and M.-H. Song, private communication,            1987.                                         Stuttgart, West Germany, in 1967 and the Ph.D.
                                                                                                                 degree    from     the University       of Minnesota,
                                                                                                                 Minneapolis,     in 1970, both in electrical engineer-
                                                                                                                     He has been on the faculty of the Department
                          chin S. Park (S’86-M87)           was born in Jeonju,                                  of Electrical     Emzineerirxz of the University      of
                          Korea, in 1955. He received the B.S. degree in                                         Minnesota     since ;970. &     teaching and rese”arch
                          electronics  from Seoul Nationaf         University    in                              interests are in the areas of circuits and systems,
                          1979, the M. S.E.E. degree from the Korea Ad-                                          filters, analog integrated    circuits, modeling,   sta-
                          vanced Institute     of Science and Technology         in   tistical circuit design, and in the realization     of fully integrated    analog
                          1981, and the Ph.D. degree from the University              filters. He has published       some 60 papers, has co-authored      the chapter
                          of Minnesota,     Minneapolis,    in 1988.                  “Active     Filters”   in Reference Data for Radio Engineers (7th Edition,
                              From 1981 to 1984 he worked for the Korea               Howard      & Sams, 1985), and is co-editor of Modern Actiue Filter Design
                          Institute of Electronics Technology in the area of          (IEEE Press, 1981).
                          LSI design, CAD, and VLSI. From 1984 to 1988                    Dr. Schaumann was the Associate Editor for Analog Signal Processing
                          he was a Research Assistant at the University          of   from     1981 to 1983 and the Editor        of the IEEE TRANSACTIONS ON
Minnesota   in the areas of high-frequency     integrated filters, analog VLSI,       CIRCUITS AND SYSTEMS from 1983 to 1985. In recent years he has been
and design centering.    He currently     is working     for Intel Corporation,       active on the Organizing        Committees   of the IEEE Intemationaf       Sym-
Santa Clara, CA. His research interests are analog integrated               system    posium on Circuits        and Systems (ISCAS);   he served on the Administra-
design, high-frequency   filters, VLSI, cell optimization,      and design auto-      tive Committee        of the CAS Society and is currently    Vice-President    for
mation.                                                                               Publications      of the CAS Society.

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