Computer Organization

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					Computer Organization
       Computer Organization
This module surveys the physical resources of a
  computer system.
   – Basic components
       I/O devices
   – CPU structure
       Processing units
   – Instruction cycle
     CPU and the Memory
The Central Processing Unit (CPU)
– responsible for instruction execution
– determines how the memory is to be modified
– contains a few data container called registers
The Main Memory
– large collection of data containers
– each is labeled with a positive integer called
  its address
For each instruction, the CPU fetches
input data from registers or memory, then
writes output to a register or memory
         Instruction Types
Arithmetic and logical instructions apply a
function to input data to produce output
– Addition, logical AND, negation
Control instructions test or compare values
of variables and make decisions about
what instruction is going to be executed
– The only output is a possible change in the
  register that keeps track of the address of the
  next instruction
Fetch-Decode-Execute Cycle
The CPU is endlessly looping through
these steps
– Actual steps will vary from processor to
MIPS R2000 steps
1. instruction fetch & PC update
2. instruction decode & operand load
3. operation execution (control instructions
  update PC)
4. memory access
         Basic Architecture
Processor (CPU)
Main Memory                CPU           Memory
– volatile
I/O devices                        System Bus

– secondary memory        Disk     Network      Serial Device
– communications        Controller Controller    Controller

– terminals
System interconnection
– a bus is used to exchange data and control
    Interconnection: the bus
Conceptually, a collection
of parallel wires, each of         data   address   control

which is dedicated to
carrying one of
– data
– address
– control (of access to the bus)
Only one component can
“write” to a particular wire
of the bus at a time
        Device Controllers

Devices are not
connected directly to
                           CPU           Memory
the system bus
Each device has a
                                   System Bus
device controller
between it and the        Disk     Network      Serial Device
system bus              Controller Controller    Controller

One controller may
have multiple devices
For example: SCSI
devices, IDE devices,
              I/O Devices
Each device has a
buffer which
mediates data           CPU         Memory
Transfer between              System Bus
memory and
devices is limited by
the size and speed              buffer
of the data bus.               Device
For example,                  Controller
though a disk reads
data to its buffer
one block at a time,
Can be viewed as a linear          231 –1
array of data values
– Indexed by non-negative
  integers: addresses
– Memory is usually byte
    each byte has its own unique
– The word-size (width of the
  data bus) of a system is often
  more than 1 byte
    Central Processing Unit
Arithmetic logic unit (ALU)
– performs arithmetic and logic operations
Control unit
– reads and decodes                                CPU
– initiates execution of        ALU          Control
  instruction by proper
  component                   PC PSW CP       SP   DL
Registers                     IR   AR DP CL        v0
– some have special purpose
                              a0   s0   s1    s2   s3
                CPU Design
CPU design defines what the computer’s
instruction do and how they are specified (the
instruction set)
The instruction set determine the computer’s
– All computers should be able to implement any logical
  function on a finite number of bits.
     Such instruction sets are said to be complete
– Not all complete designs are equal!
     Execution time may vary…
A computer’s machine language is determined
by its manufacturer
The assembly language is also formally defined
0        $zero    Value is always zero

                                                           MIPS ALU Registers
1        $at      Used by the assembler for address
2        $v0
3        $v1
                  Return values from functions
4        $a0
     …            Pass parameters to functions
7        $a3
8        $t0
     …            Caller saved register
15       $t7
16       $s0
23   …   $s7
                  Callee saved registers
24       $t8
                  More caller saved registers
25       $t9

26       $k0
                  Used by the kernel (operating system)
27       $k1

28       $gp      Global pointer
29       $sp      Stack pointer
30       $fp      Frame pointer
31       $ra      Return address (used by JAL instruction)

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