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					CprE 588
Embedded Computer Systems

  Prof. Joseph Zambreno
  Department of Electrical and Computer Engineering
  Iowa State University


  Lecture #4 – Introduction to SpecC
           Introduction
 •    System-on-Chip (SOC) design
 •    Increase of design complexity
 •    Move to higher levels of abstraction
                    Level            Number of components



                                                1E0
                 System level
                                                1E1

                  Algorithm                     1E2




                                                                       Abstraction



                                                                                     Accuracy
                                                1E3
                     RTL
                                                1E4

                                                1E5
                    Gate
                                                1E6
                  Transistor                    1E7




R. Domer, The SpecC System-Level Design Language and Methodology,
Center for Embedded Systems, University of California-Irvine, 2001.
 Feb 3-5, 2009                  CprE 588 – Embedded Computer Systems                            Lect-04.2
          The SpecC Model
                                            P1                    P2
• Traditional model                                          s1
                                                             s2
                                                             s3


      • Processes and signals
      • Mixture of computation and communication
      • Automatic replacement impossible
                                                             C1
                                            B1                    B2
• SpecC model                                                v1
                                                             v2
                                                             v3



      • Behaviors and channels
      • Separation of computation and communication
      • Plug-and-play
Feb 3-5, 2009         CprE 588 – Embedded Computer Systems        Lect-04.3
          The SpecC Model (cont.)
                                                              C1
• Specification model                        B1
                                                              v1
                                                                   B2

• Exploration model                                           v2
                                                              v3




      • Computation in behaviors
      • Communication in channels


• Implementation model                       B1
                                                              v1
                                                                   B2

                                                              v2
                                                              v3


      • Channel disappears
      • Communication inlined into behaviors
      • Wires exposed
Feb 3-5, 2009          CprE 588 – Embedded Computer Systems        Lect-04.4
          System-Level Language Goals
• Executability
   • Validation through simulation
• Synthesizability
   • Implementation in HW and/or SW
   • Support for IP reuse
• Modularity
   • Hierarchical composition
   • Separation of concepts
• Completeness
   • Support for all concepts found in embedded systems
• Orthogonality
   • Orthogonal constructs for orthogonal concepts
   • Minimality
• Simplicity
Feb 3-5, 2009       CprE 588 – Embedded Computer Systems   Lect-04.5
          System-Level Language Requirements



   Behavioral
   hierarchy
   Structural
   hierarchy
 Concurrency

Synchronization
   Exception
   handling
      Timing
      State
   transitions
   Composite
   data types

                  not supported                partially supported   supported
Feb 3-5, 2009           CprE 588 – Embedded Computer Systems            Lect-04.6
          The SpecC Language
• Foundation: ANSI-C
   • Software requirements are fully covered
   • SpecC is a true superset of ANSI-C
   • Every C program is a SpecC program
   • Leverage of large set of existing programs
   • Well-known
   • Well-established
• SpecC has extensions needed for hardware
   • Minimal, orthogonal set of concepts
   • Minimal, orthogonal set of constructs
• SpecC is a real language
   • Not just a class library
Feb 3-5, 2009       CprE 588 – Embedded Computer Systems   Lect-04.7
          The SpecC Language (cont.)
• ANSI-C                                                      /* HelloWorld.c */

      • Program is set of functions                           #include <stdio.h>

                                                              void main(void)
      • Execution starts from                                 {
                                                                printf(“Hello World!\n”);
           function main()                                    }




 • SpecC                                                      // HelloWorld.sc

                                                              #include <stdio.h>
       • Program is set of behaviors,
                                                              behavior Main
         channels, and interfaces                             {
                                                                 void main(void)
       • Execution starts from                                   {
                                                                   printf(“Hello World!\n”);
         behavior Main.main()                                 };
                                                                 }




Feb 3-5, 2009          CprE 588 – Embedded Computer Systems                         Lect-04.8
          The SpecC Language (cont.)
• SpecC types
   • Support for all ANSI-C types
                • predefined types (int, float, double, …)
                • composite types (arrays, pointers)
                • user-defined types (struct, union, enum)
      • Boolean type:
           Explicit support of truth values
                • bool b1 = true;
                • bool b2 = false;
      • Bit vector type:
           Explicit support of bit vectors of arbitrary length
                • bit[15:0] bv = 1111000011110000b;
      • Event type:
           Support for synchronization
                • event e;
Feb 3-5, 2009                  CprE 588 – Embedded Computer Systems   Lect-04.9
          The SpecC Language (cont.)
• Bit vector type                                  typedef bit[7:0] byte;     // type definition
                                                   byte             a;
   • signed or unsigned                            unsigned bit[16] b;

   • arbitrary length                              bit[31:0] BitMagic(bit[4] c, bit[32] d)
                                                   {
      • standard operators                           bit[31:0] r;

                •   logical operations                 a = 11001100b;          // constant
                                                       b = 1111000011110000ub; // assignment
                •   arithmetic operations
                                                       b[7:0] = a;            // sliced access
                •   comparison operations              b = d[31:16];

                •   type conversion                    if (b[15])             // single bit
                                                          b[15] = 0b;         // access
                •   type promotion
                                                       r = a @ d[11:0] @ c    // concatenation
      • concatenation operator                             @ 11110000b;

                •a @ b                                 a = ~(a & 11110000);   // logical op.
                                                       r += 42 + 3*a;         // arithmetic op.
      • slice operator
                                                       return r;
                • a[l:r]                           }


Feb 3-5, 2009                    CprE 588 – Embedded Computer Systems                    Lect-04.10
          The SpecC Language (cont.)
• Basic structure                 Behavior            Ports   Channel     Interfaces

      • Top behavior
      • Child behaviors                             p1
                                                               c1
                                                                          p2

                                               B
      • Channels                                               v1

      • Interfaces
      • Variables (wires)                                b1             b2

      • Ports
                                                                        Variable
                                                   Child behaviors       (wire)




Feb 3-5, 2009          CprE 588 – Embedded Computer Systems                        Lect-04.11
          The SpecC Language (cont.)
• Basic structure
       interface I1
       {
          bit[63:0] Read(void);                               p1              p2
                                                                        c1
          void Write(bit[63:0]);
       };                                                B
                                                                        v1
       channel C1 implements I1;

       behavior B1(in int, I1, out int);

       behavior B(in int p1, out int p2)                           b1        b2
       {
         int v1;
         C1 c1;
         B1 b1(p1, c1, v1),
             b2(v1, c1, p2);

            void main(void)
            { par { b1.main();
                    b2.main();
                   }
             }
       };

Feb 3-5, 2009                    CprE 588 – Embedded Computer Systems              Lect-04.12
          The SpecC Language (cont.)
• Typical test bench
  • Top-level behavior: Main
      • Stimulator provides test vectors
      • Design unit under test
      • Monitor observes and checks outputs

                Main
                                  v1                       v3
                                  v2                       v4



                 Stimulator             Design_Unit                  Monitor




Feb 3-5, 2009                 CprE 588 – Embedded Computer Systems             Lect-04.13
          The SpecC Language (cont.)
• Behavioral hierarchy
       Sequential          FSM                     Concurrent           Pipelined
       execution         execution                 execution            execution
           B_seq           B_fsm                       B_par              B_pipe
                b1       b1      b2                      b1                 b1


                b2       b3      b4                      b2                 b2


                b3       b5      b6                      b3                 b3



   behavior B_seq     behavior B_fsm            behavior B_par       behavior B_pipe
   {                  {                         {                    {
     B b1, b2, b3;      B b1, b2, b3,             B b1, b2, b3;        B b1, b2, b3;
                          b4, b5, b6;
    void main(void)     void main(void)          void main(void)      void main(void)
    { b1.main();        { fsm { b1:{…}           { par{b1.main();     {pipe{b1.main();
       b2.main();               b2:{…}                  b2.main();           b2.main();
       b3.main();               …}                      b3.main();           b3.main();
      }                  }                         }  }                 }  }
   };                 };                        };                   };
Feb 3-5, 2009              CprE 588 – Embedded Computer Systems                    Lect-04.14
          SpecC – FSM Support
• Finite State Machine (FSM)
   • Explicit state transitions
                • triple < current_state, condition, next_state >
                • fsm { <current_state> : { if <condition> goto <next_state> } … }
      • Moore-type FSM
      • Mealy-type FSM
                                                                                B_FSM
           behavior B_FSM(in int a, in int b)
           {
             B b1, b2, b3;                                      b=0
                                                                                    b>0

            void main(void)                                              b1                    b2
            { fsm { b1:{ if    (b<0) break;
                          if   (b==0) goto b1;                                      a>0
                                                                              a>b
                          if   (b>0) goto b2; }                                                 a0
                     b2:{ if   (a>0) goto b1; }
                     b3:{ if   (a>b) goto b1; }                                     b3
                   }                                                     b<0
                                                                                         ab
            }
           };


Feb 3-5, 2009                     CprE 588 – Embedded Computer Systems                                Lect-04.15
          SpecC – Pipelining Support
• Pipeline
      • Explicit execution in pipeline fashion
         • pipe { <instance_list> };      behavior                               Pipeline
                                                                  {




                                                                      Stage1 b1;
                Pipeline                                              Stage2 b2;
                                                                      Stage3 b3;

                                                                      void main(void)
                                                                      {

                                                                        pipe
                   b1      b2                b3                                { b1.main();
                                                                                  b2.main();
                                                                                  b3.main();
                                                                                }
                                                                       }
                                                                  };

Feb 3-5, 2009              CprE 588 – Embedded Computer Systems                             Lect-04.16
          SpecC – Pipelining Support (cont.)
• Pipeline
     • Explicit execution in pipeline fashion
        • pipe { <instance_list> };           behavior                     Pipeline
                                              {
        • pipe (<init>; <cond>; <incr>) { … }

                                                                   Stage1 b1;
                Pipeline                                           Stage2 b2;
                                                                   Stage3 b3;

                                                                   void main(void)
                                                                   {
                                                                      int i;
                                                                      pipe(i=0; i<10; i++)
                                                                          { b1.main();
                   b1      b2                b3                              b2.main();
                                                                             b3.main();
                                                                           }
                                                                     }
                                                                  };


Feb 3-5, 2009              CprE 588 – Embedded Computer Systems                   Lect-04.17
          SpecC – Pipelining Support (cont.)
• Pipeline
  • Explicit execution in pipeline fashion
                • pipe { <instance_list> };                            behavior Pipeline
                                                                       {
                • pipe (<init>; <cond>; <incr>) { … }                    int v1;
                                                                         int v2;
      • Support for automatic buffering                                  int v3;

                                                                        Stage1 b1(v1, v2);
                                                                        Stage2 b2(v2, v3);
                Pipeline
                                                                        Stage3 b3(v3, v1);
                                v1
                                                                        void main(void)
                           v2           v3                              {
                                                                           int i;
                                                                           pipe(i=0; i<10; i++)
                                                                               { b1.main();
                   b1           b2                b3                              b2.main();
                                                                                  b3.main();
                                                                                }
                                                                          }
                                                                       };


Feb 3-5, 2009                   CprE 588 – Embedded Computer Systems                       Lect-04.18
          SpecC – Pipelining Support (cont.)
• Pipeline
   • Explicit execution in pipeline fashion
                                                                        behavior Pipeline
                • pipe { <instance_list> };                             {
                                                                          piped piped int v1;
                • pipe (<init>; <cond>; <incr>) { … }                     piped int v2;
                                                                          piped int v3;
      • Support for automatic buffering
                                                                         Stage1 b1(v1, v2);
                • piped […] <type> <variable_list>;                      Stage2 b2(v2, v3);
                                                                         Stage3 b3(v3, v1);

                                                                         void main(void)
                Pipeline                                                 {
                                v1                                          int i;
                                                                            pipe(i=0; i<10; i++)
                           v2            v3                                     { b1.main();
                                                                                   b2.main();
                                                                                   b3.main();
                                                                                 }
                   b1           b2                 b3                      }
                                                                        };




Feb 3-5, 2009                    CprE 588 – Embedded Computer Systems                    Lect-04.19
          SpecC – Communication
• Communication
      • via shared variable
      • via virtual channel
      • via hierarchical channel

                                     C                                      C1
                 v1                         v1
     B           v2           B             v2                     B        C2
                 v3                         v3


           S           R            S                R                 S            R



            Shared memory           Message passing                    Protocol stack



Feb 3-5, 2009               CprE 588 – Embedded Computer Systems                        Lect-04.20
          SpecC – Synchronization
                                                                behavior S(out event Req,
• Synchronization                                                           out float Data,
                                                                            in event Ack)
   • Event type                                                 {
                                                                  float X;
                • event <event_List>;                             void main(void)
                                                                  { ...
      • Synchronization primitives                                  Data = X;
                                                                    notify Req;
                • wait <event_list>;                                wait Ack;
                • notify <event_list>;                              ...
                                                                  }
                • notifyone <event_list>;                       };

                                                                behavior R(in event Req,
                          Req                                               in float Data,
                                                                            out event Ack)
           B              Data                                  {
                                                                  float Y;
                          Ack                                     void main(void)
                                                                  { ...
                                                                    wait Req;
                                                                    Y = Data;
                    S              R                                notify Ack;
                                                                    ...
                                                                  }
                                                                };

Feb 3-5, 2009                    CprE 588 – Embedded Computer Systems                     Lect-04.21
          SpecC – Communication (cont.)
                                                                              interface IS
                                                                              {
• Communication                                                                 void Send(float);
  • Interface class                                                           };
                                                                              interface IR
                • interface <name>                                            {
                  { <declarations> };                                           float Receive(void);
                                                                              };
      • Channel class                                                         channel C
                • channel <name>                      behavior S(IS Port)          implements IS, IR
                  implements <interfaces>             {                       {
                  { <implementations> };                float X;                event Req;
                                                        void main(void)         float Data;
                                                        { ...                   event Ack;
                                                          Port.Send(X);
                    C                                     ...                  void Send(float X)
                            Req                                                { Data = X;
                                                        }
          B            IS   Data   IR                 };                         notify Req;
                                                                                 wait Ack;
                            Ack                       behavior R(IR Port)      }
                                                      {                        float Receive(void)
                                                        float Y;               { float Y;
                                                        void main(void)          wait Req;
                                                        {...                     Y = Data;
                   S                    R                 Y=Port.Receive();      notify Ack;
                                                          ...                    return Y;
                                                        }                      }
                                                      };                      };
Feb 3-5, 2009                       CprE 588 – Embedded Computer Systems                     Lect-04.22
          SpecC – Communication (cont.)
                                                                         interface IS
                                                                         {
• Hierarchical channel                           interface PCI_IF
                                                                           void Send(float);
                                                 {
                                                                         };
  • Virtual channel                                void Transfer(
                                                        enum Mode,
                                                                         interface IR
                                                                         {
    implemented by                                      int NumBytes,
                                                        int Address);
                                                                           float Receive(void);
                                                                         };
    standard bus protocol                        };
                                                                         channel PCI
                • example: PCI bus               behavior S(IS Port)        implements PCI_IF;
                                                 {
                                                   float X;              channel C2
                                                   void main(void)           implements IS, IR
                                                   { ...                 {
                        C2                           Port.Send(X);         PCI Bus;
                                                     ...                   void Send(float X)
        B               PCI                        }                       { Bus.Transfer(
                                                 };                              PCI_WRITE,
                                                                                 sizeof(X),&X);
                                                 behavior R(IR Port)       }
                                                 {                         float Receive(void)
                                                   float Y;                { float Y;
                  S            R                   void main(void)           Bus.Transfer(
                                                   {...                          PCI_READ,
                                                     Y=Port.Receive();           sizeof(Y),&Y);
                                                     ...                     return Y;
                                                   }                       }
                                                 };                      };
Feb 3-5, 2009                  CprE 588 – Embedded Computer Systems                     Lect-04.23
          SpecC – Miscellaneous (cont.)
• Exception handling

                Abortion                                           Interrupt
                e1    B1    e2                                      e1   B2   e2


                      b                                                  b
                 e1        e2                                       e1        e2

                a1          a2                                      i1        i2



    behavior B1(in event e1, in event e2)             behavior B2(in event e1, in event e2)
    {                                                 {
      B b, a1, a2;                                      B b, i1, i2;

     void main(void)                                   void main(void)
     { try { b.main(); }                               { try { b.main(); }
        trap (e1) { a1.main(); }                          interrupt (e1) { i1.main(); }
        trap (e2) { a2.main(); }                          interrupt (e2) { i2.main(); }
       }                                                 }
    };                                                };
Feb 3-5, 2009                    CprE 588 – Embedded Computer Systems                     Lect-04.24
              SpecC – Timing
• Timing                                                                            behavior Testbench_Driver
                                                                                             (inout int a,
                                                                                              inout int b,
         • Exact timing                                                                       out event e1,
                                                                                              out event e2)
            • waitfor <delay>;                                                      {
                                                                                      void main(void)
                                                                                      {
                                                                                       waitfor 5;
                                                                                       a = 42;
                                                                                       notify e1;
          Example: stimulator for a test bench
                                                                                         waitfor 5;
                                                                                         b = 1010b;
                                                                                         notify e2;
    in
    a ABus 0                    42     a                  43
                                                                                         waitfor 10;
    in RMode
    b           0000b                1010b        1111b        0000b                     a++;
    in WMode                                                                             b |= 0101b;
    e1                                                                                   notify e1, e2;
   inout DBus                                d
    e2                                                                                    waitfor 10;
                           0/    10/20    0/    0/          5/10
                                                                                          b = 0;
                             10/20                      10/20
                                                                                          notify e2;
          0       5   t1    10 t2    15t3    20
                                             t4    t525   t6 30 t7     35
                                                                                         }
                                                                                    };

Feb 3-5, 2009                                CprE 588 – Embedded Computer Systems                         Lect-04.25
          SpecC – Timing (cont.)
                                                                                                 Specification
• Timing
                                                                                  bit[7:0] Read_SRAM(bit[15:0] a)
   • Exact timing                                                                 {
                • waitfor <delay>;                                                  bit[7:0] d;

      • Timing constraints                                                            do { t1: {ABus = a; }
                                                                                            t2: {RMode = 1;
                • do { <actions> }                                                                WMode = 0; }
                                                                                            t3: {            }
                  timing {<constraints>}                                                    t4: {d = Dbus; }
                                                                                            t5: {ABus = 0; }
                                                                                            t6: {RMode = 0;
                Example: SRAM read protocol                                                       WMode = 0; }
                                                                                            t7: { }
                                                                                          }
     in ABus                             a                                             timing { range(t1; t2; 0;      );
                                                                                                  range(t1; t3; 10; 20);
    in RMode                                                                                      range(t2; t3; 10; 20);
                                                                                                  range(t3; t4; 0;    );
    in WMode                                                                                      range(t4; t5; 0;    );
   inout DBus                                      d
                                                                                                  range(t5; t7; 10; 20);
                                                                                                  range(t6; t7; 5; 10);
                         0/      10/20        0/        0/            5/10                      }
                              10/20                               10/20                return(d);
                    t1         t2        t3        t4        t5    t6        t7   }


Feb 3-5, 2009                                       CprE 588 – Embedded Computer Systems                          Lect-04.26
          SpecC – Timing (cont.)
                                                                                               Implementation 1
• Timing
                                                                                  bit[7:0] Read_SRAM(bit[15:0] a)
   • Exact timing                                                                 {
                • waitfor <delay>;                                                  bit[7:0] d;

      • Timing constraints                                                            do { t1: {ABus = a; waitfor( 2);}
                                                                                            t2: {RMode = 1;
                • do { <actions> }                                                                WMode = 0; waitfor(12);}
                                                                                            t3: {            waitfor( 5);}
                  timing {<constraints>}                                                    t4: {d = Dbus; waitfor( 5);}
                                                                                            t5: {ABus = 0; waitfor( 2);}
                                                                                            t6: {RMode = 0;
                Example: SRAM read protocol                                                       WMode = 0; waitfor(10);}
                                                                                            t7: { }
                                                                                          }
     in ABus                             a                                             timing { range(t1; t2; 0;      );
                                                                                                  range(t1; t3; 10; 20);
    in RMode                                                                                      range(t2; t3; 10; 20);
                                                                                                  range(t3; t4; 0;    );
    in WMode                                                                                      range(t4; t5; 0;    );
   inout DBus                                      d
                                                                                                  range(t5; t7; 10; 20);
                                                                                                  range(t6; t7; 5; 10);
                         0/      10/20        0/        0/            5/10                      }
                              10/20                               10/20                return(d);
                    t1         t2        t3        t4        t5    t6        t7   }


Feb 3-5, 2009                                       CprE 588 – Embedded Computer Systems                           Lect-04.27
          SpecC – Timing (cont.)
                                                                                              Implementation 2
• Timing
                                                                                  bit[7:0] Read_SRAM(bit[15:0] a)
   • Exact timing                                                                 {
                • waitfor <delay>;                                                  bit[7:0] d;      // ASAP Schedule

      • Timing constraints                                                            do { t1: {ABus = a; }
                                                                                            t2: {RMode = 1;
                • do { <actions> }                                                                WMode = 0; waitfor(10);}
                                                                                            t3: {            }
                  timing {<constraints>}                                                    t4: {d = Dbus; }
                                                                                            t5: {ABus = 0; }
                                                                                            t6: {RMode = 0;
                Example: SRAM read protocol                                                       WMode = 0; waitfor(10);}
                                                                                            t7: { }
                                                                                          }
     in ABus                             a                                             timing { range(t1; t2; 0;      );
                                                                                                  range(t1; t3; 10; 20);
    in RMode                                                                                      range(t2; t3; 10; 20);
                                                                                                  range(t3; t4; 0;    );
    in WMode                                                                                      range(t4; t5; 0;    );
                                                                                                  range(t5; t7; 10; 20);
   inout DBus                                      d
                                                                                                  range(t6; t7; 5; 10);
                         0/      10/20        0/        0/            5/10                      }
                              10/20                               10/20                return(d);
                    t1         t2        t3        t4        t5    t6        t7   }


Feb 3-5, 2009                                       CprE 588 – Embedded Computer Systems                            Lect-04.28
          SpecC – Miscellaneous (cont.)
• Library support
   • Import of precompiled SpecC code
                • import <component_name>;
      • Automatic handling of multiple inclusion
                • no need to use #ifdef - #endif around included files
      • Visible to the compiler/synthesizer
                • not inline-expanded by preprocessor
                • simplifies reuse of IP components

                               // MyDesign.sc

                               #include <stdio.h>
                               #include <stdlib.h>

                               import “Interfaces/I1”;
                               import “Channels/PCI_Bus”;
                               import “Components/MPEG-2”;

                               ...



Feb 3-5, 2009                   CprE 588 – Embedded Computer Systems     Lect-04.29
          SpecC – Miscellaneous (cont.)
• Persistent annotation
   • Attachment of a key-value pair
                • globally to the design, i.e. note <key> = <value>;
                • locally to any symbol, i.e. note <symbol>.<key> = <value>;
      • Visible to the compiler/synthesizer
                • eliminates need for pragmas
                • allows easy data exchange among tools

                       /* comment, not persistent */

                       // global annotations
                       note Author = “Rainer Doemer”;
                       note Date   = “Fri Feb 23 23:59:59 PST 2001”;

                       behavior CPU(in event CLK,      in event RST, ...)
                       {
                          // local annotations
                          note MaxClockFrequency =     800 * 1e6;
                          note CLK.IsSystemClock =     true;
                          note RST.IsSystemReset =     true;
                          ...
                       };
Feb 3-5, 2009                     CprE 588 – Embedded Computer Systems      Lect-04.30
          Summary
• SpecC model
   • PSM model of computation
   • Separation of communication and computation
   • Hierarchical network of behaviors and channels
   • Plug-and-play
• SpecC language
   • True superset of ANSI-C
                • ANSI-C plus extensions for HW-design
      • Support of all concepts needed in system design
                •   Structural and behavioral hierarchy
                •   Concurrency
                •   State transitions
                •   Communication
                •   Synchronization
                •   Exception handling
                •   Timing
Feb 3-5, 2009                      CprE 588 – Embedded Computer Systems   Lect-04.31
          Conclusion
• SpecC language
   • Executable and synthesizable
   • Precise coverage of system language
     requirements
   • Orthogonal constructs for orthogonal concepts
• Impact
   • Adoption of SpecC in industry and academia
   • SpecC Open Technology Consortium (STOC)
• Future
   • Standardization effort in progress by STOC
   • Improvement with your participation
Feb 3-5, 2009      CprE 588 – Embedded Computer Systems   Lect-04.32

				
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