SOC_Test_v02a.xls - ITRS

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					Table # SOC Test Short Term Technology Requirements

                Year of Production                    2001             2002             2003            2004            2005            2006
    DRAM ½ Pitch (Sc. 2.0)                           130 nm           115 nm           100 nm          90 nm           80 nm           70 nm
    MPU ½ Pitch (Sc. 3.7)                            150 nm           130nm            105 nm          90 nm           80 nm           70 nm
    MPU Printed Gate Length (Sc. 3.7)                 90 nm           75 nm            65 nm           53 nm           45 nm           40 nm

    MPU Physical Gate Length (Sc.3.7)                 65 nm           53 nm            45 nm           37 nm           32 nm           30 nm

    Fault Model
    Static Fault Model                                single          single           single          single          single        single
                                                     stuck-at        stuck-at         stuck-at        stuck-at        stuck-at     stuck-at /
                                                                                                                                  general[1]
    Delay Fault Model                               gate/path        gate/path      path delay for path delay for path delay for path delay for
                                                      delay            delay         whole chip     whole chip     whole chip     whole chip

    Fault Model for IDDQ Test                        toggle /      toggle /   pseudo-stuck- pseudo-stuck- pseudo-stuck- pseudo-stuck-
                                                  pseudo-stuck- pseudo-stuck- at / open/short at / open/short at / open/short at / open/short
                                                        at            at
    New Fault Model (crosstalk etc.)                   No            No             Yes             Yes             Yes             Yes
    New Fault Model (universal fault                   No               No               No              No              No             Yes
    model)[2]
    Test Method
    High Speed Test Using Low Speed Tester restricted use restricted use            practical use   practical use   practical use   practical use
    (on chip clock generator, test circuit on
    tester board)
    Crosstalk Test                               No             No                      Yes             Yes             Yes             Yes
    Test Strategy for IP Core-based Design           manual           manual          partially       partially       partially         fully
    (test control integration, test scheduling)                                      automated       automated       automated       automated

    Path Delay Test                               critical paths   critical paths    whole chip      whole chip      whole chip      whole chip

    IDDQ Test                                     reduced effect reduced effect      alternative     alternative     alternative     alternative
                                                                                       method          method          method          method
    Low Power Consumption Test Technique             manual           manual          partially       partially       partially          fully
    (test pattern adjustment, test scheduling)                                       automated       automated       automated       automated

    Max Frequency Validation with Low                  No               No               No              No             Yes             Yes
    Speed ATE
    DFT
    DFT at Gate Level Design (scan design)             Yes             Yes              Yes             Yes             Yes             Yes

    DFT at RTL Design (test logic insertion,         partially       partially        partially       partially         fully           fully
    testability analysis, overhead estimate)

    DFT at Higher Level Design (behavior               No               No               No              No             Yes             Yes
    level, HW/SW co-design, high level
    synthesis with testability analysis)

    DFT for Analog / Mixed-signal                 BIST[3], JTAG     BIST, JTAG       BIST, JTAG     BIST, JTAG      BIST, JTAG      BIST, JTAG

    Test Integration                                 IP-core        cost-based    cost-based            fully           fully           fully
                                                  Isolation test   DFT selection DFT selection       automated       automated       automated
                                                                                                      EDA tool        EDA tool        EDA tool
    DFT Circuits Generation (memory BIST,              Yes             Yes              Yes             Yes             Yes             Yes
    logic BIST, JTAG)
    BIST
    Embedded Memory BIST                          restricted use   practical use    practical use   practical use   practical use   practical use

    Embedded Memory BIST (redundant               restricted use restricted use         Yes             Yes             Yes             Yes
    configuration, self repair)

    Logic BIST                                    restricted use      Yes [4]          Yes [4]         Yes [4]         Yes [4]         Yes [4]
                                                   for stuck-at
                                                      faults

    Analog/Mixed Signal BIST                      restricted use restricted use restricted use      limited use     limited use       full use
                                                      (PLL)           (PLL,          (PLL,             (PLL,           (PLL,
                                                                   ADC,etc.)      ADC,etc.)          ADC,etc.)       ADC,etc.)
Others
Standardization
Test Data[5]                                     Standard       Standard       Standard                   Standard           Standard     analog data
                                                Format on      Format on      Format on                  Format on          Format on
                                                   EDA            EDA          EDA/ATE                    EDA/ATE            EDA/ATE
Test Method/Test Interface[6]                    Standard       Standard       Standard                   Standard           Standard      automated
                                              Methods on IP Methods on IP Methods on IP               Methods on IP      Methods on IP      SOC test
                                                   core           core            core                   core/ EDA          core/ EDA      integration
Fault Model/Fault Coverage[7 ]                Single Stuck- Single Stuck- standard fault               standard fault     standard fault new standarad
                                              at Fault Model at Fault Model models, SOC                models, SOC        models, SOC fault model, its
                                                                            level coverage            level coverage     level coverage     coverage



Test Cost
Test Time Reduction                           for SCAN test for SCAN test for SCAN test                for IP core-       for IP core- new approach
                                                                                                      based design       based design    for huge
                                                                                                                                          design

Faulty Chip Repair (memory BISR)                    No                 No                    Yes            Yes                   Yes        Yes
Faulty Chip Repair (logic BISR, etc.)               No                 No                    No              No                   No         No

Failure Analysis
IDDQ-based Failure Analysis                        Yes                Yes                    Yes            Yes                   Yes        Yes
Chip Backside Analysis                             Yes                Yes                    Yes            Yes                   Yes        Yes
Integrated Diagnostics / Failure Analysis           No                Yes                    Yes            Yes                   Yes        Yes
Environments
Test Generation for Failure Analysis                No                Yes                    Yes            Yes                   Yes        Yes

Failure Analysis for Analog Circuits                No                 No                    No              No                   No         No

BIST Pattern Exchange Technique[8]                  No                 No                    No              No                   No         No




White–Manufacturable Solutions Exist, and Are Being Optimized
Yellow--Manufacturable Solutions are Known
Red–Manufacturable Solutions are NOT Known


Table notes below:
For clarification--use an asterisk*, double asterisk*, etc. [*, **, ***, §, † , ‡, ƒ] for in the Table above and in table notes
For a series of technical notations or definitions--use a Capital Letter in both the Table above and at the beginning of
a series of technical notations/definitions




1: Fault model for more realistic defects.
2: An abstruct fault model for evaluating total test quality for various types of defects.
3: Restricted use for PLL
4: high fault coverage, at-speed test on system operation, test time restraint, low power, low area overhead
5: The standardization of test data format needs to reduce turn-around-time of Test Program development.
6: The standardization of test method and test interface(Wrapper) needs to popularize IP Cores.
7: The standardization of fault model and fault coverage needs to popularize IP Cores.
8:A kind of reseeding or programming technique for diagnosing escaped defective LSIs, which failed in field.



Work-in-Progress--Do Not Publish
     2007         Driver
    65 nm
    65 nm
    35 nm

    25 nm



    single
  stuck-at /
 general[1]
path delay for
 whole chip

pseudo-stuck-
at / open/short

     Yes
     Yes



practical use



     Yes
     fully
  automated

 whole chip

  alternative
    method
      fully
  automated

     Yes



     Yes

     fully



     Yes




 BIST, JTAG

     fully
  automated
   EDA tool
     Yes



practical use

     Yes



   Yes [4]




   full use
 analog data



  automated
   SOC test
  integration
new standarad
fault model, its
   coverage




new approach
  for huge
   design

      Yes
      No



      Yes
      Yes
      Yes

      Yes

      No

      No
Table # SOC Test Long Term Technology Requirements

                       Year of Production                          2010                    2013                    2016            Driver
    DRAM ½ Pitch (Sc. 2.0)                                        45 nm                   32 nm                   22 nm
    MPU ½ Pitch (Sc. 3.7)                                         45 nm                   32 nm                   22 nm
    MPU Printed Gate Length (Sc. 3.7)                             25 nm                   18 nm                   13 nm
    MPU Physical Gate Length (Sc.3.7)                             18 nm                   13 nm                    9 nm
    Fault Model
    Static Fault Model                                       single stuck-at /       single stuck-at /       single stuck-at /
                                                                 general                 general                 general
    Delay Fault Model                                      path delay for whole    path delay for whole    path delay for whole
                                                                   chip                    chip                    chip
    Fault Model for IDDQ Test                               pseudo-stuck-at /       pseudo-stuck-at /       pseudo-stuck-at /
                                                                open/short              open/short              open/short
    New Fault Model (crosstalk etc.)                               Yes                     Yes                     Yes
    New Fault Model (universal fault model)                        Yes                     Yes                     Yes
    Test Method
    High Speed Test Using Low Speed Tester (BIST              practical use           practical use           practical use
    with on chip clock generator, test circuit on tester
    board)
    Crosstalk Test                                                 Yes                     Yes                     Yes
    Test Strategy for IP Core-based Design (test control     fully automated         fully automated         fully automated
    integration, test scheduling)
    Path Delay Test                                            whole chip              whole chip              whole chip
    IDDQ Test for Low-Vth Circuit                          alternative method      alternative method      alternative method

    Low Power Consumption Test Technique (test               fully automated         fully automated         fully automated
    pattern adjustment, test scheduling)
    Max Frequency Validation                                       Yes                     Yes                     Yes
    DFT
    DFT at Gate Level Design (scan design)                         Yes                     Yes                     Yes
    DFT at RTL Design (test logic insertion, testability           fully                   fully                   fully
    analysis, overhead estimate)
    DFT at Higher Level Design (behavior level,                    Yes                     Yes                     Yes
    HW/SW co-design, high level synthesis with
    testability analysis)
    DFT for Analog / Mixed-signal                              BIST, JTAG              BIST, JTAG              BIST, JTAG
    Test Integration                                       fully automated EDA     fully automated EDA     fully automated EDA
                                                                    tool                    tool                    tool
    DFT Circuits Generation (memory BIST, logic                     Yes                     Yes                     Yes
    BIST, JTAG)
    BIST
    Embedded Memory BIST                                      practical use           practical use           practical use
    Embedded Memory BIST (redundant configuration,                 Yes                     Yes                     Yes
    self repair)
    Logic BIST                                                     Yes                     Yes                     Yes
                                                                    [*1]                    [*1]                    [*1]
    Analog/Mixed Signal BIST                                     full use                full use                full use
    Others                                                 tester on chip, logic   tester on chip, logic   tester on chip, logic
                                                                   BISR                    BISR                    BISR
    Standardization
    Test Data                                                  analog data             analog data             analog data
    Test Method/Test Interface                             automated SOC test      automated SOC test      automated SOC test
                                                               integration             integration             integration
    Fault Model/Fault Coverage                             new standarad fault     new standarad fault     new standarad fault
                                                           model, its coverage     model, its coverage     model, its coverage

    Test Cost
    Test Time Reduction                                     new approach for        new approach for        new approach for
                                                              huge design             huge design             huge design
    Faulty Chip Repair (memory BISR)                              Yes                     Yes                     Yes
    Faulty Chip Repair (logic BISR, etc.)                          Yes                     Yes                     Yes
    Failure Analysis
    IDDQ-based Failure Analysis                                    Yes                     Yes                     Yes
    Chip Backside Analysis                                         Yes                     Yes                     Yes
    Integrated Diagnostics / Failure Analysis                      Yes                     Yes                     Yes
    Environments
Test Generation for Failure Analysis                              Yes                         Yes                          Yes
Failure Analysis for Analog Circuits                              Yes                         Yes                          Yes
BIST Pattern Exchange Technique                                   Yes                         Yes                          Yes



White–Manufacturable Solutions Exist, and Are Being Optimized
Yellow--Manufacturable Solutions are Known
Red–Manufacturable Solutions are NOT Known


Table notes below:
For clarification--use an asterisk*, double asterisk*, etc. [*, **, ***, §, † , ‡, ƒ] for in the Table above and in table notes
For a series of technical notations or definitions--use a Capital Letter in both the Table above and at the beginning of
a series of technical notations/definitions
1: high fault coverage, at-speed test on system operation, test time restraint, low power, low area overhead




Work-in-Progress--Do Not Publish

				
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posted:10/2/2011
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