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12 AP_December 2006 ITRS .ppt

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					International Technology Roadmap
        for Semiconductors


      Assembly and Packaging
               2006



              ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   1
     Assembly and Packaging Roadmap 2006
                  Participants
      W. R.Bo tto m s - Ch a ir                                                                  Willia m Ch e n -Co -Ch a ir
              Un ite d   S ta te s                       J apan                      Eu ro p e                    S in g a p o re
Abha y Ma he s hwa ri    Ke ith Ne wma n        Eiji Yos hida               Be rnd Appe lt                 Kripe s h Va idya na tha n
Bob P fa hl              Kis hor De s a i       He nry Uts unomiya          Be rnd Roe me r
Cha rle s Re ynolds      Le i Me rca do         Hirofumi Na ka jima         Coe n Ta k
Chi-S hih Cha ng         Luu Nguye n            His a o Ka s uga            G ille s P oupon                         Ko re a
Bob Chyla k              Ma rio Bola nos        Ka zuo Nis hiya ma          Kla us P re s s e l            J a s on Cho
De be ndra Ma llik       Ma rtin Ba ye s        Ma s a na o Ya no           Ma x J ue rge n Wolf           Choon He ung Le e
G e orge Ha rma n        Muha nna d Ba kir      Michita ka Kimura           Ra lf P lie ninge r            Dongho Le e
Ha rold.Hos a ck         Ra lph K. Ca vin       Nobuo Futa wa ta ri         J e a n-P ie rre Mos cicki     Kwa ng Yoo Byun
J a me s Bird            Richa rd Arnold        Ryo Ha ruta                                                S onjin Cho
J a me s Wilcox          S ta n Mihe lcic       S hige ki Ue da                     Ta iw a n              Yong-Bin S un
J os e ph Ada m          Voya Ma rkovich        S hige ru Uts umi           Ca rl Che n
Zhiping Ya ng            S us a n Vitka va ge   S hoji Ue ga ki             Mike Hung
                                                S huya Ha ruguchi           Rongs he n Le e
                                                Ta ka s hi Ta ka ta         Clinton Cha o
                                                                            S e ba s tia n Lia u



                                                    ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan        2
ITRS A&P Chapter Organization

   Scope
   Difficult Challenges
   Technical Requirements
   Infrastructure Challenges
   Potential Solutions
   Tables



              ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   3
Assembly and Packaging Roadmap
                       2006


   Packaging has become the limiting element in
    system cost and performance
   The Assembly and packaging role is expanding
    to include system level integration functions.
   As traditional Moore’s law scaling become more
    difficult innovation in assembly and packaging
    can take up the slack.




                    ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   4
 Assembly and Packaging Emerging as
Limiting Factor for Cost and Performance

 Consumers now drive more than half of integrated
  circuit revenue
 Assembly and Packaging technology is a primary
  differentiator for consumer electronics
 These factors are driving an unprecedented pace of
  innovation in:
   ▬ New Materials
   ▬ New Technologies
   ▬ New Systems Integration



                        ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   5
               Assembly and Packaging
The pace of change in several areas is faster than anticipated

   System in a package (SiP) has become the structure of choice
    for many consumer products with new requirements for package
    design, materials, processing and test access
   Wafer thinning has progressed to a level requiring special
    handling and assembly processes
   Stacked die package layer count is increasing rapidly requiring
    new methods for bonding, testing, etc.




                              ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   6
    Packaging Technology Challenges

                             Interconnect Scaling
                          Connect Si features (nm) to
                          circuit board features (cm)


High Speed Signaling                                                        Power Delivery
Facilitate distortion –                                                    Efficiently deliver
   free signaling                                                        Power to enable high
                                                                         speed Si performance



                               Power Removal
                            Efficiently duct away
                              dissipated power




                                 ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   7
    New Packaging Technologies
   Thinned wafers
   3D systems integration
   Wafer level packaging
   Bio-chips
   Integrated optics
   Embedded/integrated active and passive devices
   MEMS
   Printable circuits
    ▬   Semiconductors
    ▬   Light emitters
    ▬   RF
    ▬   Interconnect
   Flexible (wearable) electronics




                     ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   8
   Systems Integration in the Cellular Phone
        It is not only integrated circuits
                                       Embedded Antenna                                              Camera Circuit
     LCD Circuit                  •Smaller・Stability of signal                                       •Smaller
                                   •Influence on the human body
•Larger display, Color                                                                               •Lower power consumption
display                                                                                              •One unit of lens and control
•Lower power                                                                                         circuit
consumption
•Higher resolution
                                                                                                             Memory Circuit
                                                                                                        •Memory area for
                                                                                                        downloaded software
DSP・CPU・BB                                                                                              •Higher memory capacity
•Dual CPU: Transmission
/Application
                                                                                                         Plug In Memory Card
                                                                                                            •Smaller, thinner
        Tx、Rx Circuit                                                                                   •Higher memory capacity

•Smaller & lower power                                                                         Outer Interface Circuit
consumption of analog circuit
                                                                                                        •Bluetooth, USB interface
•Decrease of # of mounted                       Power Supply
components                                                                                                   •MP3, GPS interface
                                                   Circuit
                                                                                                          •Memory Card interface
                                                  •Smaller Size

                         Source: H.Ueda JEITA       ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   9
SiP: Multi-level System Integration
     SiP may include SoC and other traditional packages




Packages may include:
Sub-system packages
Stacked thin packages containing passives and active chips
Mechanical, optical and other non electrical functions
Complete systems or sub-systems with embedded components
Bare die

      Source: Fraunhofer IZM   ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   10
                         Categories of SiP

    Horizontal Placement
                                               Wire Bonding Type                         Flip Chip Type


             Interposer Type
                                                        Wire Bonding +
Stacked                               Wire Bonding Type Flip Chip Type                        Flip Chip Type
Structure

            Interposer-less Type
                                                          Terminal Through Via Type



                                       Chip (WLP) Embedded +                             3D Chip Embedded
    Embedded Structure                 Chip on Surface Type                              Type


                                                    WLP Embedded + Chip on Surface Type




                                               Hitachi, Conference 2006 The Ambassador Hotel Hsin
                   Source: 20030710 K. Nishi, ITRS WinterJEITA, Revised by H. Utsunomiya Chu        Taiwan   11
     Applications for Flip Chip based SiP


                     Notebook                                             Tablet PC


                                              Chip Set
                                                                                                        Web Pad

                     CPU                                                         Graphic


                                              Flip Chip
Set Top Box
                Communication                                                      NIC


                                                 DSP

                                                                                                 Cell phone


              PC
                                  DSC                                     PDA

       Package substrate is the key issue for Flip Chip
              Source: IEK/ITRI)    ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan         12
          Assembly and Packaging
           There are significant revisions to tables


 Difficult Challenges
   ▬ Pb free transition presents cost, reliability and process
     compatibility problems that are not resolved
   ▬ A new generation of DFM and DFT will be required for
     complex SiP and SoC packaging
   ▬ Stress induced changes in electrical properties for very thin
     die
   ▬ Reliability for through wafer vias and die layer bonding
   ▬ Warpage control for stacked die
   ▬ Interconnect for nano-scale structures
   ▬ Self assembly for very small die




                           ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   13
          Significant Table Revisions
                            Continued

 Many new Materials are required for the emerging
  package requirements:
   ▬ Improved thermal conductivity for dielectrics and materials
     interfaces
   ▬ Molding compounds compatible with copper and other new
     materials
   ▬ Improved resistance to electromigration as temperature and
     current density continue to rise
   ▬ Dielectrics with improved fracture toughness and interfacial
     adhesion
   ▬ Green materials that meet regulatory, cost and reliability
     requirements




                             ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   14
                New Materials
Most, if not all, packaging materials will change
                 within this decade

            Cu interconnect
            Ultra Low k dielectrics
            High k dielectrics
            Organic semiconductors
            Green Materials
            ▬   Pb free
            ▬   Halogen free
            ▬   other



                   ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   15
            Assembly and Packaging
         Technical working Group 2006 Focus
     We are giving special focus in 2006 to preparation of a white
     paper titled:

       “The next step in Assembly and Packaging:
                             Systems Level Integration”

Objectives of this white paper
   Catalyze additional SiP chapter for 2007 ITRS issue
   Identify needs and gaps
   Identify new technology trends for future SiP




                              ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   16
“The next step in Assembly and Packaging:
                Systems Level Integration”


Introduction & Motivation
 The basic elements generic to all SiP System level
  integration applications will be defined.

 Examples will be used from various application
  areas to show how the basic elements are
  incorporated into these applications.




                      ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   17
 Critical updates to selected sections in
           preparation for 2007


 Expansion of the section on handling and
  packaging of extremely thin die

 Expanded treatment of sensors in
  cooperation with iNEMI




                  ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   18
              In Preparation for 2007

 “More than Moore”
   ▬ SiP
      • At the limit Camera, wireless, logic, memory, display, data entry
        (human interface), location (GPS), sensors (accelerometers),
        security, MEMS
      • Lower cost, smaller size, lower power, higher performance
   ▬ 3D packaging
      • TSV and laminated layers
   ▬ System integration (including thermal management)
   ▬ Embedded passive and active devices
   ▬ Power subsystems
   ▬ Wafer level packaging



                             ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   19
3D Packaging increases Performance Density
    and enables system level integration
                                                   New System in Package (SIP)
            Sibley                                     solutions enables rapid
  256M NAND                                            integration of different
   Sibley
              Spacer                                          functions

Wire bonded stacked die             Communications

                          Computing                         Memory


                                                                 z
                                      Package
                               x                        y

      Small form factor for
   ultramobile PCs, hand-helds,
     phones & other consumer
            electronics
                                                                                    Thru-Si via Stacking

                                   ITRS Winter Conference 2006   The Ambassador Hotel Hsin Chu Taiwan   20

				
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