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Presentation kit A Reconfigurable Design for Debug Infrastructure for

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					 A Reconfigurable Design-for-Debug
      Infrastructure for SoCs

 Miron Abramovici     Peter Levin
   Paul Bradley     Gerard Memmi
Kumar Dwarakanath     Dave Miller
Silicon Debug: Growing Barrier to Market Entry

          Spec            RTL               Netlist        1st Si     Debug &
                                                                     Qualification
180nm
 $4.2M                                                                               ~ 17% of
~12 mo                                                                                 TTM



130nm
$10.8M                                                                                          > 28% of
~15 mo                                                                                            TTM !



 90nm
$25.8M                                                                                                 > 35% of
~18 mo                                                                                                  TTM ?


                          Traditional Debug Strategies Failing
         Source: Collett ASIC/IC Verification Study 2004 (180nm / 130nm)
  Post-Silicon Debug Problem Statement

 1st Silicon often doesn’t work
      More than 50% of new chips have functional issues
      After substantial and expensive pre-silicon verification


 Post-silicon debug is expensive
      Average debug and validation period (at 90nm): 6 months
      Economic impact of delayed ramp to production: $ tens
       of millions

 Post-silicon debug is challenging
      Very limited observability of chip-internal signals
      On-chip clock frequency often too high for external
       access
         In-System At-Speed Silicon Debug
 Required to validate silicon
                                             Application program
 Exercises functionality and timing not
  verified pre-silicon
 More constrained than tester-based
  debug
 Expected values not known
 The problem may be caused by a
  defect
                                                 SoC Under Debug
 Problem difficult to reproduce on tester
 State-of-the-art
      Ad-hoc debug structures
      Time-consuming manual effort
      Few commercially available tools
                    A New Approach

 Distributed reconfigurable infrastructure fabric
      User-guided insertion compatible with existing design
       flows
      Soft IP inserted at RTL
      Configured post-silicon for maximum debug flexibility


 Effective debug and verification platform
      Signal capture and analysis
      Assertion-based debug
      Stimulate and capture
      What-if analysis
      Event- and transaction-driven debug support
                  Design Flow Integration

                       Insert
                  Instrumentation

                                                        Synthesis
                                                      Physical Design
                                          Prototype
Customer Design                             Silicon
                              Debug
                            Environment
                                               
                                           Accelerated
                                           Debug &
                                           Validation
                 Debug Structures
 Configured dynamically (when needed):
    triggers to start/stop recording of signals
    assertion checkers
    event detectors
    event counters
    pattern generators
    value injectors
   …
   …


 Configuration and instrument control via JTAG TAP
              Instrumented Chip Example
 Signal Probe
  Network
  (transport/selection)
 DEbug MONitor
  (analysis)
 Tracer
  (capture)
 Wrapper
  (analysis & control)
 CapStim
  (capture/stimulate)
 JTAG
 Primary CONtroller
  (instrumentation
  access & control)
        Tapping / Wrapping of Signals

                                   Net_a
BEFORE




                TAP                                 WRAP

                Net_a                      Net_a               <X>_Net_a
AFTER                                                    MUX



                        Delay: none                                 Delay: 1 MUX
                        Load: 1 Gate                                Load: 1 Gate
                        TAP: þ                                      TAP: þ
          MUX           WRAP: ¨                                     WRAP: þ
                        OBS: þ                  Wrap                OBS: þ
                        SCTL: ¨                Element              SCTL: þ
                        ASCTL: ¨                                    ASCTL: þ
                        MOD: ¨                                      MOD: þ
           Supported Debug Paradigms
 Signal capture and logic analysis
 Assertion-based debug
 Stimulate and capture (in-situ, at-speed IP
  verification)
 Event- and transaction-driven debug
 Scan-based debug
 What-if analysis
      Fault/error injection
      Soft fixes or ECOs


May be intermixed
Signal Probe Network (SPN)

        Pipeline register
         for enhanced
             speed

                               FIFO
                        for clock domain
                             crossing

                            Daisy chain
                            for ease-of
                              routing




                                  Aligner
                               for data path
                                 balancing
Logic Analysis and Signal Capture

                       DEMON block
                        implements triggers
                       Signals captured by
                        Tracer
                       Software reads trace
                        buffer and prepares
                        VCD or FSDB files
                         Monitors




Reconfigurable Monitor
 more flexible              Programmable Trigger Engine
                              less area
                              higher speed
               CAPSTIM Instrument
 Used for in-situ IP verification
           Assertion-Based Silicon Debug
 Assertions
      Properties that must be true in a correct circuit
      Extensively used in pre-silicon verification
 Benefits
      Automatic continuous checks
      Significant reduction in search space for root-cause


 Implement assertions in silicon
      Configure instrumentation with assertions
          User-defined assertions
          Library of pre-set assertions
 Benefits
      Automatic continuous checks
      Significant reduction in search space for root-cause
                  Implementing Assertions
 Use DEMONs and
  wrappers
 Assertions run at
  speed
 Concurrent assertions
 Large number of
  assertions can be run
  by reusing the fabric
  for different groups
 No need for expected
  values
 Help identifying
  transient or deep-state
  functional issues
Configuring Assertions

                  Personality Editor
                  Pre-set library
                       50+ assert functions
                  Verilog compiler
            What Signals To Instrument
 Tap signals identifying important transactions
 Identify high-risk areas
      new IP cores
      new user-defined logic
      logic with poor verification coverage
      logic for new or evolving standards
 Tap signals likely to expose errors
  (signals of interconnected high-risk FSMs)
 Tap input signals for assertions in high-risk areas
 Wrap signals likely to be modified
      for what-if experiments
      for soft-fixes or ECOs
      for fault/error injection
                    Infrastructure Investment
Tapped    Wrapped
                    PTE     Tracer   SPN     Wrap    Example:
Signals   Signals
  1,024     102     1.16%   0.16%    0.11%   0.96%
                                                        5M user gates
  4,096     409     1.16%   0.16%    0.37%   3.84%      10% ratio tapped/wrapped
  8,192     819     1.16%   0.16%    0.74%   7.68%
                                                        32bit debug bus
                                                        PTE with 16 states / 4
                                                         branches



                                                     Observability:
                                                      8192 signals tapped
                                                       2.1% additional gates
                                                     Observability & Control
                                                      819 signals wrapped
                                                       7.7% additional gates
                      Conclusions
 A new approach to silicon debug
      Reconfigurable debug infrastructure
      On-chip observability and control
      Support for many different debug paradigms
 Advantages
      Enables in-system at-speed debug and validation
      Repeatedly configured for different debug structures
      Accelerates debug in the lab and in the field
      Eliminates the need for multiple respins
 Other applications
      Performance measurements
      On-line testing
      …
      …

				
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