Documents
Resources
Learning Center
Upload
Plans & pricing Sign in
Sign Out

Test and Test Equipment - ITRS

VIEWS: 2 PAGES: 21

									Test and Test Equipment
July 2010
San Francisco, USA

Roger Barth - Micron
ITRS Test TWG




        ITRS 2010 Test and Test Equipment – San Francisco, USA
      2010 Test Team
Akitoshi Nishimura                 Jody Van Horn                     Sanjiv Taneja
Amit Majumdar                      John YS Kim                       Satoru Takeda
Anne Gattiker                      Kazumi Hatayama                   Sejang Oh
Atul Goel                          Ken Lanier                        Shawn Fetterolf
Bill Price                         Ken Taoka                         Shoji Iwasaki
Burnie West                        Ken-ichi Anzou                    Stefan Eichenberger
Calvin Cheung                      Khushru Chhor                     Steve Comen
Chris Portelli-Hale                Masaaki Namba                     Steve Tilden
Dave Armstrong                     Masahiro Kanase                   Steven Slupsky
Davide Appello                     Michio Maekawa                    Takairo Nagata
Dennis Conti                       Mike Bienek                       Takuya Kobayashi
Erik Volkerink                     Mike Peng Li                      Tetsuo Tada
Francois-Fabien Ferhani            Mike Rodgers                      Tom Williams
Frank Poehl                        Paul Roddy                        Ulrich Schoettmer
Gibum Koo                          Peter Maxwell                     Wendy Chen
Hirofumi Tsuboshita                Phil Nigh                         Yasuo Sato
Hiroki Ikeda                       Prasad Mantri                     Yervant Zorian
Hisao Horibe                       Rene Segers                       Yi Cai
Jeong Ho Cho                       Rob Aitken
Jerry Mcbride                      Roger Barth


                                                                                           2
            ITRS 2010 Test and Test Equipment – San Francisco, USA
2009 Changes
•   DFT
     – Test data compression and test time potential solutions identified
     – Major rewrite completed of the Design Chapter DFT section
•   Test Cost
     – Test cost survey completed that quantifies industry view
     – Test parallelism dependency by device type modified based on I/O count
•   Adaptive Test
     – New chapter section shows necessity for adaptive test to lower cost
•   Prober
     – Complete redo of prober table to address parallelism and power
•   Probecard
     – LCD display driver probe added as driver
•   Handler
     – Added 10-50 Watt handler category
•   Test Sockets
     – Socket BW limitations on current sockets
     – New future contacting solutions are required

                                                                                3
          ITRS 2010 Test and Test Equipment – San Francisco, USA
2010 Drivers                                                          Unchanged

• Device trends                                                        Revised

   –   Increasing device interface bandwidth and data rates              New

   –   Increasing device integration (SoC, SiP, MCP, 3D packaging)       Drop

   –   Integration of emerging and non-digital CMOS technologies
   –   Device characteristics beyond the deterministic stimulus/response
       model
   –   Fault Tolerant architectures and protocols
   –   3 Dimensional silicon - multi-die and Multi-layer
   –   Multiple Power modes and Multiple time domains
   –   Complex package electrical and mechanical characteristics
• Test process complexity
   –   Adaptive test and Feedback data
   –   Concurrent test within a DUT
   –   Maintaining unit level test traceability
   –   Device customization / configuration during the test process
   –   “Distributed test” to maintain cost scaling
                                                                           4
         ITRS 2010 Test and Test Equipment – San Francisco, USA
Drivers                                                             Unchanged
                                                                     Revised
                                                                      New
• Economic Scaling of Test
                                                                      Drop
   –   Physical limits of packaged test parallelism
   –   Test data volume
   –   Managing interface hardware and (test) socket costs
   –   Multiple Insertions and System test
   –   Effective limit for speed difference of HVM ATE versus DUT
   –   Trade-off between the cost of test and the cost of quality




                                                                        5
         ITRS 2010 Test and Test Equipment – San Francisco, USA
2010 Difficult Challenges
•   Test for yield learning
     – Critically essential for fab process and device learning below optical device
       dimensions
                                                                                   Unchanged
•   Detecting Systemic Defects                                                      Revised
     – Testing for local non-uniformities, not just hard defects                       New
     – Detecting symptoms and effects of line width variations, finite dopant
                                                                                       Drop
       distributions, systemic process defects


•   Screening for reliability
     – Effectiveness and Implementation of burn-in, IDDQ, and Vstress testing
     – Detection of erratic, non deterministic, and intermittent device behavior




                                                                                         6
           ITRS 2010 Test and Test Equipment – San Francisco, USA
                                                                      Unchanged
2010 Difficult Challenges                                              Revised
                                                                         New
                                                                         Drop

• Potential yield losses
    – Tester inaccuracies (timing, voltage, current, temperature control,
      etc)
    – Over testing (e.g., delay faults on non-functional paths)
    – Mechanical damage during the testing process
    – Defects in test-only circuitry or spec failures in a test mode e.g.,
      BIST, power, noise
    – Some IDDQ-only failures
    – Faulty repairs of normally repairable circuits
    – Decisions made on overly aggressive statistical post-processing




                                                                                7
         ITRS 2010 Test and Test Equipment – San Francisco, USA
Test Cost Components




                                                             8
    ITRS 2010 Test and Test Equipment – San Francisco, USA
Adaptive Test
                                                        •     Modify testing based on
                                                              analysis of previous results
                                                               –   Real-time
                                                               –   Near-time
                                                               –   Off-line
                                                        •     Benefits
                                                               –   Higher Quality
                                                               –   Fast Test Time Reduction
                                                               –   Lower cost
                                                               –   Fast yield learning
                                                        •     Requires data infrastructure
                                                               –   Database
                                                               –   Analysis tools  Confidence
                                                        •     Implementation is evolving
                                                               –   Multiple learning steps
                                                               –   Delaying won’t ease task




                                                                                          9
     ITRS 2010 Test and Test Equipment – San Francisco, USA
Test Parallelism Changes




•   Soc, Low Performance Logic, commodity DRAM and Commodity Flash unchanged

                                                                               10
           ITRS 2010 Test and Test Equipment – San Francisco, USA
SoC Changes




• Fault models pulled in Bridging faults to 2011
• Full ATE standardized interface delayed from 2013 to 2015
• DFT based defect analysis has slightly extended life


                                                                 11
        ITRS 2010 Test and Test Equipment – San Francisco, USA
Memory Changes




• Data rates pulled in thru 2016


                                                                 12
        ITRS 2010 Test and Test Equipment – San Francisco, USA
    RF Changes




•   Increase in short term Carrier Frequency for 2010
•   Limited need for 12 GHz requirements…
•   20GHz appears to be small volume as compared to other
    devices…may be lack of developed instrumentation
•   Target is now 60+ GHz (personal networks and SR radar)

                                                                     13
            ITRS 2010 Test and Test Equipment – San Francisco, USA
Probing Technology Changes




•   2011 memory roadmap will separate DRAM and Flash in table
•   Low contact force probing process requirement added to roadmap
                                                                     14
          ITRS 2010 Test and Test Equipment – San Francisco, USA
Prober Characteristics

                                             •    Many changes / additions
                                                  from 2008 tables
                                                   –   Probe card dimensions
               2009                                –   Test head weight
                                                   –   Temperature accuracy
                                                   –   450mm wafer support
                                                   –   Chuck leakage
                                                   –   Planarity
                                                   –   Etc.


                                             •    Solutions exist until 2014
                 2008
                                                                DRIVERS
                                                              Full wafer test
                                                              Device Power

                                                                                15
     ITRS 2010 Test and Test Equipment – San Francisco, USA
3D Devices
• Multiple die system
   – Sub-systems designed to operate and be
     assembled together
   – Process optimized for contents of each die
       • Logic, DRAM, NVM, Analog
   – Connection by potentially 1000’s of TSVs
     (Thru Silicon Via’s)

• Design, Interconnect, Assembly and Test,
  PIDS and FEP problem

• DFT Requirements
   – Testability of each die
   – Vias cannot be probed due to ESD issues
   – N+ die test methodology a possibility as                    void
     die added, not recommended
   – Final 3D Packaged test



                                                                        16
        ITRS 2010 Test and Test Equipment – San Francisco, USA
TSV Test Strategy
•   Strong Recommendations
    – Can’t (and don’t) touch the TSVs.
        • Alternative test pads with ESD protection are ok (analog, power, digital)
        • Use Boundary scan test for access
    – Design independently testable die
        • Cannot require resources from other die for test
        • Need not operate in mission mode
    – Design low resistance TSVs
    – TSV geometry and parametrics are not be the critical technology limiter
•   Needs
    – Thermal considerations needed for scan after stack
    – Optimal functional / performance / system test
    – Possible benefit to self Speed Test (SST) thru TSV loop (post stack)
•   Trends
    – System test / validation much more important in the future with TSVs. The
      die stack is a system.


                                                                                      17
         ITRS 2010 Test and Test Equipment – San Francisco, USA
Test Time Reduction Potential Solutions




• Required test time reduction is driven by SoC
• Assumes increasing design complexity and transistor count will
  not increase test time


                                                                   18
         ITRS 2010 Test and Test Equipment – San Francisco, USA
DFT Compression Potential Solutions




•   Development is necessary to get very high levels of data compression
•   Demonstrated techniques are just approaching 1000x
•   100k data compression necessary out in time…no clear path yet!

                                                                           19
          ITRS 2010 Test and Test Equipment – San Francisco, USA
High Speed Interfaces




                                                              Jitter Test Critical for HS
                                                                       Interfaces


                                                                   Test Sockets are not
     •   Bit bandwidth increasing…                                    able to support
     •   Physical limit?                                           controlled impedance
                                                                   contacts at >15 GT/s
     •   Test limit?
                                                                                        20
     ITRS 2010 Test and Test Equipment – San Francisco, USA
Summary of 2010 table (trend) Changes
• Device Trends and Challenges significantly updated

• Minor adjustments to tables
   –   Test parallelism
   –   SoC
   –   Memory
   –   Probing Technology


• Refinement of TSV testing strategy




                                                                  21
         ITRS 2010 Test and Test Equipment – San Francisco, USA

								
To top