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ESE535_ Electronic Design Automation Warmup Poll Modern

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EDA in the communications industry (telecommunications) in Another explanation is that the enterprise data architecture, EDA gives an enterprise-level view of the overall data architecture, and in accordance with the characteristics of the telecommunications company to carry out the framework and the division level. Electronic design automation EDA stands in the mid-1960s from computer-aided design (CAD), computer-aided manufacturing (CAM), computer-aided test (CAT) and computer-aided engineering (CAE) developed the concept of come.

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									                   ESE535:
        Electronic Design Automation                                                               Warmup Poll
                                                                     •  How many of you have:
                                                                          –  Drawn geometry for transistors and wires
                                                                          –  Sized transistors
                                                                          –  Placed logic and/or memory cells
                        Day 1: January 12, 2011                           –  Selected the individual gates
                                                                          –  Specified the bit encoding for an FSM
                              Introduction                                –  Designed a bit-slice for an Adder or ALU
                                                                          –  Written RTL Verilog or VHDL
  Complete questionnaire                                                  –  Written Behavioral Verilog, VHDL, etc. and compiled
                                                                             to hardware?
                                                                          –  Compiled C to gates?
Penn ESE535 Spring2011 -- DeHon                              1   Penn ESE535 Spring2011 -- DeHon                                        2




                                                                                          Productivity Gap
             Modern Design Challenge
       •  How do we design modern
          computational systems?
            –  billions of devices
            –  used in everything
            –  billion dollar businesses
            –  rapidly advancing technology
            –  more “effects” to address
            –  rapidly developing applications and uses
            –  short product cycles
            –  extreme time-to-market pressures
Penn ESE535 Spring2011 -- DeHon                              3   Penn ESE535 Spring2011 -- DeHon      Source: ITRS2009 Design Chapter   4




                  The Productivity Gap
                                                                                                    Bottleneck
                                                                        •  Human brain power is the bottleneck
                                                                             –  to producing new designs
                                                                             –  to creating new things
                                                                                  •  (applications of technology)
                                                                             –  to making money




                                     Source: Newton (UCB/GSRC)
Penn ESE535 Spring2011 -- DeHon                              5   Penn ESE535 Spring2011 -- DeHon                                        6




                                                                                                                                            1
                                                                                                          Design Productivity by
                              Avoiding the Bottleneck                                                           Approach       GATES/WEEK
                                                                                                                                                             (Dataquest)
                                                                                                DOMAIN
       •  How do we unburden the human?                                                         SPECIFIC
                                                                                                                                                               8K - 12K
                –  Take details away from him/her
                              •  raise the level of abstraction at which human              BEHAVIORAL
                                                                                                                                                               2K - 10K
                                 specifies computation
                                                                                                    RTL                                                        1K - 2K
                –  Pick up the slack
                                                                                                                                       a   0   d

                              •  machine take over the details                                                                         b   1
                                                                                                                                                         q


                                                                                                                                                               100 - 200
                                                                                                   GATE                                    s       clk




                                                                                            TRANSISTOR                                                          10 - 20


Penn ESE535 Spring2011 -- DeHon                                                     7    Penn ESE535 Spring2011 -- DeHon      Source: Keutzer (UCB EE 244)                  8




                To Design, Implement, Verify
                      10M transistors                                                                            Central Questions
                                       Staff Months
                                        62.5                                                    •  How do we make the machine fill in the
                                        125                                                        details (elaborate the design)?
   Beh
                                                                                                •  How well can it solve this problem?
                                         625
   RTL                                                                                          •  How fast can it solve this problem?
            a
            b
                0
                1
                    d
                               q         6250
                s       clk
                                                                 Power

                                        62,500                              Delay




                                                                         Area
Penn ESE535 Spring2011 -- DeHon          Source: Keutzer (UCB EE 244)               9    Penn ESE535 Spring2011 -- DeHon                                                   10




                                                                                                                           Instructor
                                               Outline                                          •  VLSI/CAD user + Novel Tech. consumer
                                                                                                     –  Architect, Computer Designer
                                                                                                     –  Spatial designs: FPGAs, Reconfigurable
       •    Intro/Setup
                                                                                                     –  Hybrid: Multicontext FPGAs, P+FPGA
       •    Instructor                                                                               –  Nanoscale: CNT, NW-based, NEMS
       •    The Problem                                                                              –  Avoid tedium (impatient)
       •    Decomposition                                                                       •  Analyze Architectures
                                                                                                     –  necessary to explore
       •    Costs
                                                                                                     –  costs different (esp. in new technologies)
       •    Not Solved
                                                                                                •  Mapping as part of runtime?
       •    This Class                                                                               –  Variation, wear, reliability

Penn ESE535 Spring2011 -- DeHon                                                     11          •  Requirements of Computation
                                                                                         Penn ESE535 Spring2011 -- DeHon                                                   12




                                                                                                                                                                                2
                                   Problem                                                 Problem: Specification
       •  Map from a problem specification down                                 •  Recall: basic tenant of CS theory
          to an efficient implementation on a                                        –  we can specify computations precisely
          particular computational substrate.                                        –  Universal languages/building blocks exist
       •  What is                                                                         •  Turing machines
            –  a specification                                                            •  nand gates

            –  a substrate                                                      •  EEs:
            –  have to do during mapping                                             –  Can build any function out of nand gates
                                                                                     –  Any FSM out of gates + registers

Penn ESE535 Spring2011 -- DeHon                                     13   Penn ESE535 Spring2011 -- DeHon                            14




                              Specifications                                                               Substrate
                                                                                •    “full” custom VLSI
       •    netlist                     •  RTL                                  •    Standard cell
       •    logic gates                      –  Register Transfer
                                                Level                           •    metal-only gate-array
       •    FSM                                                                 •    FPGA
                                             –  (e.g. subsets of
       •    programming                         Verilog, VHDL)                  •    Processor (scalar, VLIW, Vector)
            language                    •    behavioral
            –  C, C++, Lisp, Java,
                                                                                •    Array of Processors (SoC, {multi,many}core)
               block diagram            •    dataflow graph                     •    billiard balls
       •  DSL (domain specific)         •    layout                             •    Nanowire PLA
            –  MATLAB, Snort            •    SPICE netlist                      •    molecules
                                                                                •    DNA
Penn ESE535 Spring2011 -- DeHon                                     15   Penn ESE535 Spring2011 -- DeHon                            16




                                  Full Custom                                                               FPGA
       •  Get to define all
          layers                                                              K-LUT (typical k=4)
       •  Use any geometry                                                     Compute block
          you like                                                               w/ optional
       •  Only rules are                                                      output Flip-Flop
          process design rules
       •  ESE570


                                                                              ESE171, CIS371
Penn ESE535 Spring2011 -- DeHon                                     17   Penn ESE535 Spring2011 -- DeHon                            18




                                                                                                                                         3
                                                                                                                 Nanowire PLA
                       Standard Cell Area
                                                                  All cells
                                                                  uniform
              inv nand3 inv          AOI4         nor3    Inv
                                                                  height

                                                                  Width of
                                                                  channel
                                                                  determined
                                                                  by routing

                                  Cell area              Width of channel
                                                         fairly constant?
Penn ESE535 Spring2011 -- DeHon                                               19   Penn ESE535 Spring2011 -- DeHon                                     20




            What are we throwing away?
            (what does mapping have to                                                              Specification not Optimal
                     recover?)
                                                                                          •  Y = a*b*c + a*b*/c + /a*b*c

       •    layout                            •  Cycle-by-cycle
       •    TR level circuits                    timing
                                                                                          •  Multiple representations with the same
       •    logic gates / netlist             •  Operation
                                                                                             semantics (computational meaning)
       •    FSM                                  sequencing
                                              •  How task
                                                                                          •  Only have to implement the semantics,
       •    Allocation of                                                                    not the “unimportant” detail
            functional units and                 implemented
            assignment                        DSL: MATLAB                                 •  Exploit freedom to make
Penn ESE535 Spring2011 -- DeHon                                               21
                                                                                               – 
                                                                                   Penn ESE535 Spring2011 -- DeHon
                                                                                                                            /faster/cooler
                                                                                                                      smaller
                                                                                                                                                       22




                                                                                                                                     Behavioral
                                                                                                                                  (C, MATLAB, …)

                        Problem Revisited                                                                      Decomposition              Arch. Select
                                                                                                                                          Schedule
                                                                                                                                       RTL
                                                                                                                                          FSM assign
       •  Map from some “higher” level down to                                     •  Conventionally, decompose into phases:              Two-level,
          substrate                                                                     –  Arch. select, scheduling, assignment -> RTL
                                                                                                                                          Multilevel opt.
                                                                                                                                           Covering
       •  Fill in details:                                                              –  sequential opt. -> logic equations              Retiming

            –  device sizing, placement, wiring, circuits,                              –  logic opt., covering -> gates             Gate Netlist
                                                                                        –  retiming -> gates and registers                 Placement
               gate or functional-unit mapping, timing,                                                                                    Routing
               encoding, data movement, scheduling,                                     –  placement-> placed gates
                                                                                                                                       Layout
               resource sharing                                                         –  routing->mapped design
                                                                                   •  Good abstraction, manage complexity
                                                                                                                                      Masks
Penn ESE535 Spring2011 -- DeHon                                               23   Penn ESE535 Spring2011 -- DeHon                                     24




                                                                                                                                                            4
              Easy once decomposed?                                                                      Decomposition
  •  All steps are (in general) NP-hard.                                                 Easier to solve
       –  routing                 NP-hard:                                               –  only worry about one problem at a time
       –  placement                Can verify solution in polytime
                                        N, N2, N100
                                                                                         Less computational work
       –  partitioning
                                   Do not know how to find in polytime                   –  smaller problem size
       –  covering
       –  logic optimization
                                           only known eN                               Abstraction hides important objectives
                                    if there were a polytime solution
       –  scheduling                                                                     –  solving 2 problems optimally in sequence
                                         then P=NP
                                                                                            often not give optimal result of
  •  What do we do about NP-hard problems?
                                                                                            simultaneous solution
       –  Return to this problem in a few slides…

Penn ESE535 Spring2011 -- DeHon                                         25   Penn ESE535 Spring2011 -- DeHon                                       26




                                                                                                               Costs
          Mapping and Decomposition
                                                                                    •  Once get (preserve) semantics, trying to
                                                                                       minimize the cost of the implementation.
       •  Two important things to get back to                                            –  Otherwise this would be trivial
                                                                                         –  (none of the problems would be NP-hard)
            –  disentangling problems
                                                                                    •  What costs?
            –  coping with NP-hardness                                              •  Typically: EDA [:-)]
                                                                                         –  Energy
                                                                                         –  Delay (worst-case, expected….)
                                                                                         –  Area
                                                                                    •  Future
                                                                                         –  Yield
                                                                                         –  Reliability
                                                                                         –  Operational Lifetime
Penn ESE535 Spring2011 -- DeHon                                         27   Penn ESE535 Spring2011 -- DeHon                                       28




                                  Costs                                                         Costs: Area vs. Delay
       •  Different cost critera (e.g. E,D,A)
            –  behave differently under transformations
            –  lead to tradeoffs among them
                 •  [LUT cover example next slide]
            –  even have different optimality/hardness
                 •  e.g. optimally solve delay covering in poly time,
                    but not area mapping
                      – E.g. covering

                                                                                                Example of exploiting freedom of mapping choice.
Penn ESE535 Spring2011 -- DeHon                                         29   Penn ESE535 Spring2011 -- DeHon                                       30




                                                                                                                                                        5
                                                                                  Costs may also simplify
                                  Costs                                                  problem
                                                                           •  Often one cost dominates
       •  Cannot, generally, solve a problem                                    –  Allow/supports decomposition
          independent of costs                                                  –  Solve dominant problem/effect first (optimally)
            –  costs define what is “optimal”                                   –  Cost of other affects negligible
            –  e.g.                                                                  •  total solution can’t be far from optimal
                 •  (A+B)+C vs. A+(B+C)                                         –  e.g.
                 •  [cost=pob. Gate output is high]                                  •  Delay in gates,
                 •  A,B,C independent                                                •  Delay in wires

                 •  P(A)=P(B)=0.5, P(C)=0.01                                    –  Require: formulate problem around relative costs
                 •  P(A)=0.1, P(B)=P(C)=0.5                                •  Simplify problem at cost of generality

Penn ESE535 Spring2011 -- DeHon                                31   Penn ESE535 Spring2011 -- DeHon                                     32




                   Coping with NP-hard
                        Problems                                                        Not a solved problem
       How do we cope with?                                            Why need to study – not just buy tool from C or M?
       •  simpler sub-problem based on dominant cost                   •  NP-hard problems
          or special problem structure
                                                                            –  almost always solved in suboptimal manner
       •  problems exhibit structure
                                                                            –  or for particular special cases
            –  optimal solutions found in reasonable time in
               practice                                                •  decomposed in suboptimal ways
       •  approximation algorithms                                     •  quality of solution changes as dominant costs
            –  Can get within some bound of optimum                       change
       •  heuristic solutions                                               –  …and relative costs are changing!
       •  high density of good/reasonable solutions?                   •  new effects and mapping problems crop up with
            –  Try many … filter for good ones                            new architectures, substrates
       •  …makes it a highly experimental discipline
Penn ESE535 Spring2011 -- DeHon                                33   Penn ESE535 Spring2011 -- DeHon                                     34




                              Big Challenge                                This Class: Student Outcomes
                                                                        •  You will learn:
       •  Rich, challenging, exciting space
                                                                             –  Freedom exists in design mappings and how to
       •  Great value                                                           exploit
            –  practical                                                     –  Formulate & abstract optimization problems
            –  theoretical                                                   –  How to decompose large problems
                                                                             –  Techniques for attacking these problems
       •  Worth vigorous study                                               –  Traditional design objectives (e.g. E,D,A, map time.)
            –  fundamental/academic                                          –  Canonical representations for problems
            –  pragmatic/commercial                                          –  Evaluate the quality of a design mapping
                                                                             –  Implement design automation algorithms
Penn ESE535 Spring2011 -- DeHon                                35   Penn ESE535 Spring2011 -- DeHon                                     36




                                                                                                                                             6
                                                                                                                     Behavioral
                                                                   This Class:                                    (C, MATLAB, …)
        This Class: Technique Toolkit                              Decomposition                                          Arch. Select
                                                                                                                          Schedule
                                                                                                                       RTL
       •    Dynamic Programming                                                                                           FSM assign
       •    Linear Programming (LP, ILP)                               •    Provisioning                                  Two-level,
       •    Graph Algorithms                                           •    Scheduling                                    Multilevel opt.
                                                                                                                          Covering
       •    Greedy Algorithms                                          •    Logic Optimization                            Retiming
       •    Randomization                                                                                          Gate Netlist
                                                                       •    Covering/gate-mapping                         Placement
       •    Search                                                                                                        Routing
       •    Heuristics                                                 •    Partitioning
                                                                                                                      Layout
       •    Approximation Algorithms                                   •    Placement
       •    SAT                                                        •    Routing                                   Masks
Penn ESE535 Spring2011 -- DeHon                            37   Penn ESE535 Spring2011 -- DeHon                                       38




                                                                                          Graduate Class
                  Student Requirements                                •  Assume you are here to learn
                                                                            –  Motivated
       •  Reading
                                                                            –  Mature
       •  Class
                                                                            –  Not just doing minimal to get by and get a
       •  Projects                                                             grade
            –  Will involve programming algorithms                    •  Not plug-in-numbers and get solution
            –  Roughly weekly                                         •  Things may be underspecified
            –  Cumulative build toward an overall                           –  Reason
               mapping goal
                                                                            –  Ask questions
            –  Choose what you do for final piece
                                                                            –  State assumptions
                 •  Last month
Penn ESE535 Spring2011 -- DeHon                            39   Penn ESE535 Spring2011 -- DeHon                                       40




                                  Materials                                                       Administrivia
       •  Reading
            –  Online                                                  •  Return Info sheets
                 •  several on blackboard
                 •  Rest on Xplore, ACM DL, web                        •  Feedback – every lecture – return@end
                     – Linked from syllabus page                       •  Web page
            –  If online, linked to reading page on web;                    –  http://www.seas.upenn.edu/~ese535/
               I assume you will download/print/read.                       –  Policies on web page
            –  Possible reference texts (on web)                                 •  READ THIS (you are responsible for knowing)
       •  Lecture slides                                                    –  Syllabus linked off page (reading, assign)
            –  I’ll try to link to web page by 10am                    •  Next Class Wed. 19th
                 •  you can print                                           –  Monday is MLK holiday
Penn ESE535 Spring2011 -- DeHon                            41   Penn ESE535 Spring2011 -- DeHon                                       42




                                                                                                                                            7
                                                                            Today’s Big Ideas
                                  Questions?
                                                           •    Human time limiter
                                                           •    Leverage: raise abstraction+fill in details
                                                           •    Problems complex (human, machine)
                                                           •    Decomposition necessary evil (?)
                                                           •    Implement semantics
                                                                –  Exploit freedom to xform to reduce costs
                                                           •  Dominating effects
                                                           •  Problem structure
                                                           •  Optimal solution depend on cost
                                                              (objective)
Penn ESE535 Spring2011 -- DeHon                43   Penn ESE535 Spring2011 -- DeHon                           44




                                                                                                                   8

								
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