Memory

Document Sample
Memory Powered By Docstoc
					                       PPT/2K804/04
         Revision no.: PPT/2K403/02




Memory
                                                                                                                                                   Revision no.: PPT/2K804/04



Classification

• Memory is classified primarily into two parts i.e. primary
  storage and secondary storage.




     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



Classification                                  (contd.)




• Primary Storage is further classified into two types i.e. ROM
  and RAM.

• Secondary storage contains the different devices such as
  Floppy disk, Hard disk, Zip disk and DAT cartridge.

• Memory normally refers to the amount of RAM installed in the
  computer.

• Leading companies which are the memory suppliers are
  Micron, Siemens etc.

     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



Primary Storage Devices

• Primary Storage Device types available are
   – ROM (Read Only Memory)

   – RAM (Random Access Memory)

• ROM (Read Only Memory)
   – ROM is where data is stored permanently. Hence it is also called
       as Non Volatile Memory.

   – ROM chip works necessitates the programming of complete data
       when the chip is created.



     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                  Revision no.: PPT/2K804/04



Primary Storage Devices (contd.)


   – ROMs use very little power, are extremely reliable and, contain all

      the necessary programming to control the device.

   – Different types of ROM are

          • PROM (Programmable Read only Memory).

          • EPROM (Erasable Programmable Read only Memory).

          • EEPROM (Electrically Erasable Programmable Read Only Memory).




    © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



PROM


• It is basically a blank ROM chip that can be written to, but only

  once.

• A jolt of static electricity can easily cause fuses in the PROM to

  burn out, changing essential bits from 1 to 0.

• It is much like a CD-R drive that burns the data into the CD.



     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



EPROM


• It is just like PROM, except that you can erase the ROM by

   shining a special ultra-violet light into a sensor on top of the

   ROM chip for a certain amount of time.

• The ultra-violet light used is at a particular frequency that will

   not penetrate most plastics or glasses, and each EPROM chip

   has a quartz window on top of it.

• EPROM eraser is not selective, it will erase the entire EPROM.

     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



EEPROM


• EEPROM chip does not have to removed to be rewritten.

• The entire chip does not have to be completely erased to

  change a specific portion of it.

• Instead of using UV light, you can return the electrons in the

  cells of an EEPROM to normal with the localized application of

  an electric field to each cell.


     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



Flash Memory


• Flash memory is actually a variation of electrically erasable

  programmable read-only memory (EEPROM).

• Flash memory devices are high density, low cost, nonvolatile,

  fast (to read, but not to write), and electrically reprogrammable.

• Big difference between EEPROM and Flash is that EEPROM

  can be erased and rewritten at the byte level whereas flash

  memory can erase or reprogram blocks of bytes, not individual

  bytes, hence it is faster.

     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                  Revision no.: PPT/2K804/04



RAM (Random Access Memory)

• RAM is considered "random access" because one can access
  any memory cell, which is the basic unit of data storage, in the
  same amount of time.

• RAM is a volatile memory, meaning all data is lost when power
  is turned off.

• Programs are loaded before the CPU processes the
  information into the RAM.

• RAM is used for temporary storage of program data.

    © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



RAM Basics

• In dynamic random access memory
  (DRAM), a transistor and a capacitor are
  paired to create a memory cell, which
  represents a single bit of data.
• The transistor acts as a switch that lets
  the control circuitry on the memory chip
  read the capacitor or change its state.
• Charge on the capacitors used in RAM is
  constantly refreshed so as to keep the
  information within it and hence the name
  Dynamic RAM.

     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



Writing Operation

• Initial phase of writing data to a particular cell in RAM consists
  of first activating the address line that is connected to cell
  through an electrical pulse.
• When the transistor is turned on, the operating system sends
  bursts of signals along the consecutive data line that
  represent 0 or one which is found in cells sequentially.
• When an electrical pulse from the data reaches a transistor
  that is activated by an address line, the transistor switches on
  and allows current to pass through, thus charging the
  capacitor connected to it.
     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                  Revision no.: PPT/2K804/04



Types of Memory Packages


DIP( Dual in line package)

• Found in older pc's, 286, 386.

• Each memory chip is fitted into the individual
  socket.

ZIP (Zigzag Inline Package)

• All of the connectors were on one side, allowing the
  memory package to rest on its side.

    © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                  Revision no.: PPT/2K804/04



Form Factor

•  Memory chips are mounted on green circuit
   boards called memory module.
• These modules are fitted on memory packages.
SIPP (Single Inline Pin Package)
• SIPP is a small circuit board containing several
   memory chips and has a single row of pins
   across the bottom.
• SIPP memory has tiny pins instead of an edge
   connector.


    © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                  Revision no.: PPT/2K804/04



SIMM (Single in line memory module)

• It comprises a little circuit board on which chips are mounted.

• The circuit board fits into a Memory Slot on the Motherboard in

  the same way as graphics card or any other card is fitted.
• SIMM's are of two types 30 pin and 72 pin,

• 386 and 486-SX used 30 pin SIMMs, 486-DX PCI chipset and

  Pentium use 72 pin SIMMs.




    © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                  Revision no.: PPT/2K804/04



DIMM (Dual Inline Memory Module)


DIMM has connectors on both sides of the module
•   They are of 168 pin.
•   Used for SDRAM.

SO-DIMM (Small Outline DIMM)

•   Commonly used in notebook computers.

•   It is smaller than the 168-pin DIMM and is
    available in either 72 or 144-pin configurations.

    © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                  Revision no.: PPT/2K804/04



RIMM (RAMBUS Inline Memory Module)

• Implemented for RDRAM.
• It is proprietary of ASUS motherboards
• It is a 184-pin module offering faster access and
  transfer speed, and thus generate more heat.
PC Cards, SmartMedia etc.
• These are small, thin modules that plug into a
  special socket found mostly on notebook
  computers, digital cameras, and Personal Digital
  Assistants (PDAs).
    © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                  Revision no.: PPT/2K804/04



Memory Speed

•   When the CPU needs information from memory,
    it sends out a request that is managed by the
    memory controller.
•   The memory controller sends the request to
    memory and reports to the CPU when the
    information will be available for it to read.
•   Entire cycle - from CPU to memory controller to
    memory and back to the CPU - can vary in
    length according to memory speed as well as
    other factors, such as bus speed.
    © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                  Revision no.: PPT/2K804/04



Memory Speed (contd.)


•   Memory speed is sometimes measured in

    Megahertz (MHz), or in terms of access time

•   The actual time required to deliver data -

    measured in nanoseconds (ns). Is called as

    access time.


    © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                  Revision no.: PPT/2K804/04



Access Time (Nanoseconds)

•   Access time measures from, when the memory
    module receives a data request to, when that
    data becomes available.

•   Memory chips and modules used to be marked
    with access times ranging from 80ns to 50ns.

•   With access time measurements lower numbers
    indicate faster speeds

    © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                  Revision no.: PPT/2K804/04




Example
•   The memory controller requests data from memory and
    memory reacts to the request in 70ns.
•   The CPU receives the data in approximately 125ns.
•   The total time from when the CPU first requests
    information to when it actually receives the information
    can be up to 195ns using a 70ns memory module.
•   It takes time for the memory controller to manage the
    information flow, and the information needs to travel from
    the memory module to the CPU on the bus
    © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                 Revision no.: PPT/2K804/04




MEGAHERTZ & SYSTEM CLOCK

MEGAHERTZ (MHZ) [millions of cycles per second]
• Beginning with Synchronous DRAM technology,
  memory chips had the ability to synchronize
  themselves with the computer's system clock
SYSTEM CLOCK
• A computer's system clock resides on the
  motherboard.
• It sends out a signal to all other computer
  components in rhythm, like a metronome.
• This rhythm is typically drawn as a square wave


   © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                  Revision no.: PPT/2K804/04



SYSTEM CLOCK (contd.)


•   If a system clock runs at 100MHz, that means
    there are 100 million clock cycles in one second.
•   Every action in the computer is timed by these
    clock cycles, and every action takes a certain
    number of clock cycles to perform
•   It's possible for the CPU and other devices to
    run faster or slower than the system clock.
•   Components of different speeds simply require
    a multiplication or division factor to synchronize
    them.
    © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                 Revision no.: PPT/2K804/04



Types of RAM


  – Two categories

         • DRAM (dynamic RAM)

         • SRAM (static RAM)




   © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



DRAM

• Uses tiny capacitors to store charge corresponding to digitals
  0s and 1s since capacitors always required dynamic
  refreshing.
• Types of DRAM

             1) FPM                                                                                          5) DDR RAM
             2) EDORAM                                                                                       6) RDRAM
             3) SDRAM                                                                                        7) SGRAM
             4) ECC DRAM                                                                                     8) VRAM




     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



FPM (Fast Page Mode) RAM


• A type of RAM that allows faster access if the data being called

  is in the same row as the data previously requested.

• Also called page mode memory.

• First memory chips to use the burst mode timing, wherein data

  is read 32 bytes at a time one after the other.

• Typical of processors from 8088/86 - 486.


     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



EDORAM


• It send data while data was being written in to it independently.

• This RAM is used from 80286 class machine till Pentium class

  machines.

• It can not operate on a bus speed faster than 66MHz.

• It works at 3.3V.

• It is available with pin configuration of either 30 pins or 72

  pins.

     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



SDRAM


• Synchronous DRAM is best suited to PII / PIII class computer

  due to its 100 and 133 MHz operating speed.

• This RAM consists of two separate internal bank of transistors

  for storing data.

• One bank of data can be accessed while the other is getting

  ready thus streamlining the data


     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



ECC DRAM

• Many higher-end systems use a special type of RAM called
  error correction code (ECC) DRAM.

• NON-ECC is normally used by the end users.

• NON-ECC RAM checks out for any error occurred in parity bit,
  but does not correct it, which is performed by ECC

• ECC detects problems in RAM quite well and can fix most of
  them on the fly.

• ECC RAM are costly as compared with NON -ECC RAM

     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



DDR (Double Data Rate RAM)


• Similar to SDRAM operating at double speed of system bus of

  SDRAM

• high data transfer rate at 1.066GB/sec.

• DDR doubles the throughput without increasing the clock

  frequency.

• The maximum clock frequency remains at 133 MHz


     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



DDR working

• The technology in DDR plays with the way data is transferred.



                             Data transfer in SDRAM                                             Data transfer in DDR
                              happens on the rising                                           SDRAM happens on the
                             edge of the clocks pulse                                        rising and falling edges of
                                                                                                   the clock pulse


• Clock frequency can be represented as a square wave.
• This has a rising edge, a high-plane, a falling edge, and a low-
  plane.



     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



DDR working (contd.)


• In conventional SDRAM, one bit of data is transferred during

  the rising edge of the clock cycle.

• Since the rising edge gets all the data, the falling edge

  performs nothing in SDRAM.

• In DDR RAM the falling edge performs a ‘bit’ of data transfer.

• Resulted in two bits of data being transferred per clock cycle,

  essentially doubling the transfer rate.

     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



DDR vs SDRAM

• DDR memory also fits into DIMM (Dual In-line Memory Module)
  slots, although the pin count is different.

• SDRAM has 168 pins

• DDR consists of 184 pins.

• You can buy DDR memory and fit it in your existing
  motherboard with SDRAM.

• DDR reduced power consumption.

• SDRAM consumes 3 volts per signal

     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                  Revision no.: PPT/2K804/04



DDR vs SDRAM (contd.)


• DDR takes just 2.5 volts.

• Lower power requirements can help increase the
  battery backup time in notebooks.

• Motherboard chipsets have to be designed to
  support DDR as well as SDRAM.

• Many manufacturers provide this support for eg:-
  Micron Samurai and AMD 760 chipsets.

    © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



DDR vs SDRAM (contd.)                                                                                                                                          Cont….




• DDR memory mostly used into high-end graphics workstations

  or high-end server systems with multiple CPUs.


• This lets several users share the same system, and at the

  same time giving them dedicated devices and memory space.




     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



RD RAM (Rambus Inline Memory Module)

• Rambus DRAM generally designed for AMD's CPU's, Intel's
  copper mine, with speed up to 800MHz of teams

• Data transferring rates reaching 1.66B/sec.

• RDRAM offers high performance because of increased
  operational frequency

• Three versions of it are intended: PC 600 (clock speed:
  300MHz), PC700 (actually 711 or 356MHz), and PC 800
  (400MHz).

     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



RD RAM (contd.)


• RIMMs can develop hot spots apparently related to their speed

  of operation, each RIMM has a heat spreader cover plate to try

  to diffuse the heat.

• RDRAM RIMMs comes in 2 sizes: 184 pin for desktops and 160

  pins SO RIMM for laptops.

• RIMMs can't be used on motherboards not designed with

  Rambus sockets in place.

     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



SGRAM

• It is streamlined to work with graphics cards.

• Enables fast read and write operation for the graphics
  processor when working with the information in the Video
  frame buffer.

VRAM (Video RAM)

• Memory that is optimized for Video Cards where each memory
  cell is dual ported.

• Video data can be written to the RAM while the graphics
  adapter simultaneously reads from it to refresh the display.
     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



SRAM


• Its the fastest type of RAM.

• It is expensive to fabricate.

• Storing of each bit requires several transistor.

• No refreshing required

• Classified as
           • Core RAM

           • Cache RAM



     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



Cache Memory


• Cache memory is a relatively small amount (normally less than

  1MB) of high speed memory that resides very close to the

  CPU.

• Cache memory is designed to supply the CPU with the most

  frequently requested data and instructions.

• Retrieving data from cache takes a fraction of the time that it

  takes to access it from main memory.

• Having cache memory can save a lot of time.
     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



Cache Memory                                         (contd.)




• Caches are organized into layers.

• The highest layer is closest to the device (such as the CPU)

  using it.

• There are two levels of cache built right into the CPU.

• Any cache memory component is assigned a "level" according

  to its proximity to the processor.


     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



Cache Memory                                         (contd.)




• The cache that is closest to the processor is called Level 1 (L1)
  Cache.
• The next level of cache is numbered L2, then L3, and so on.
• Hit Rate
• Whenever the CPU finds the data it needs in the cache then it
  is called a cache hit.
• When the CPU fails to find the data it needs in the cache that is
  called a cache miss.
• The ratio of cache hits to cache misses is called that is called
  a cache hit ratio.

     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



Layers Of Cache

• Each layer of cache is closer to the processor and faster than
  the layer below it.
• Each layer also caches the layers below it, due to its increased
  speed relative to the lower levels.




     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



Level 1 (Primary) Cache


• Level 1 or primary cache is the fastest memory on the PC.

• It is built directly into the processor itself.

• It is very small, generally from 8 KB to 64 KB, but it is

   extremely fast and runs at the same speed as the processor.




     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



Level 2 (Secondary) Cache


• Level 2 cache is a secondary cache to the level 1 cache, and is

  larger and slightly slower.

• Used to catch recent accesses that are not caught by the level

  1 cache, and is usually 64 KB to 2 MB in size.

• Usually found either on the same package as the processor

  itself (though it isn't in the same circuit where the processor

  and level 1 cache are) or on the motherboard or as a

  daughterboard that inserts into the motherboard.

     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



Level 2 (Secondary) Cache (contd.)

• Write Through and Write Back :
• When the CPU writes new data to the cache, the cache
  controller must update main memory with the new data.
• By making sure that the information in the cache is the same
  as that in main memory the cache controller is said to maintain
  cache coherency.
• If the cache controller allows the data in the cache to differ
  from data in main memory, the data is said to be stale.
• Every time the CPU updates the cache, the data is
  automatically written through to the main memory. Which is
  called as write through cache.


     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



Level 2 (Secondary) Cache (contd.)

• If the CPU needs to access the cache or main memory before
  the write through is completed, the CPU must wait.
• This will slow the overall performance of the CPU.
• To prevent this problem the cache controller update a small
  but fast buffer instead of directly updating the main memory.
• Because the buffer can be faster than the main memory, the
  cache controller can make the cache available to the CPU
  sooner.
• This method of updating the main memory is called a Buffered
  or posted write through.

     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                                   Revision no.: PPT/2K804/04



Level 2 (Secondary) Cache (contd.)


• The cache controller will keep track of which data is stale and

  only update the memory when it must, not immediately

  required after every memory write. This technique is called

  write back or copy back.

• The concept of buffering, or posting, the writes can also be

  applied to the write back cache to further increase its

  performance as well.

• It results in the fastest cache.

     © CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
                                                                                                                                              Revision no.: PPT/2K804/04




                                                    Design & Published by:
      CMS Institute, Design & Development Centre, CMS House, Plot No. 91, Street No.7,
                                         MIDC, Marol, Andheri (E), Mumbai –400093,
                                                           www.cmsinstitute.co.in

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute

				
DOCUMENT INFO
Shared By:
Stats:
views:20
posted:9/23/2011
language:English
pages:49