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EGR 277 – Digital Logic_22_

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									Lecture #22        EGR 260 – Circuit Analysis
Read: Chapter 9 and Appendix B in Electric Circuits, 8th Edition by Nilsson

Using Phasors to Add Sinusoids
Sinusoidal voltages or currents could be added using various trigonometric identities;
however, they are more easily combined using phasors.

Example: If v1 = 10cos(200t + 15), v2 = 15cos(200t + -30), and v3 = 8sin(200t),
find v4.
       +    V2       _

 +                         +
 V1                        V3
 _                         _

       +      V4     _



                                                                                  1
Lecture #22       EGR 260 – Circuit Analysis
sin(wt) or cos(wt)?
Since phasor analysis is used to calculate results that are relative to the sources, it
generally doesn’t matter whether the sinusoidal source is expressed using sin(wt) or
cos(wt). If the sources are expressed using sin(wt), then the results will also be in
terms of sin(wt) and if the sources are expressed using cos(wt), then the results will
also be in terms of cos(wt). However, the approach for a given circuit containing
multiple sources must be consistent – either using cos(wt) or sin(wt).


Review of DC Circuit Analysis Techniques
Analyzing AC circuits is very similar to analyzing DC resistive circuits. Several
examples are presented below which will also serve to review many DC analysis
techniques, including:
• Source transformations
• Mesh equations
• Node equations
• Superposition
• Thevenin’s and Norton’s theorems
• Maximum Power Transfer theorem
                                                                                     2
Lecture #22      EGR 260 – Circuit Analysis
Source transformations
A phasor voltage source with a series impedance may be transformed into a phasor
current source with a parallel impedance as illustrated below. The two sources are
identical as far as the load is concerned.
Notes:
• Not all sources can be transformed. Discuss.
• The two sources are not equivalent internally. For example, the voltage across
  Zs is not equivalent to the voltage across Zp.
• Dependent sources can be transformed.
                         I                                        I
                  Zs
                          +                                        +
           +
           _
      Vs                  V   Load             Ip          Zp      V   Load
                          _                                        _




 Converting a real current source              Converting a real voltage source
 to a real voltage source:                     to a real current source:
 V s  I p  Z p and   Zs  Z p                       Vs
                                               Ip       and    Z p  Zs
                                                      Zs                          3
Lecture #22         EGR 260 – Circuit Analysis
Example: Solve for the voltage V using source transformations.
                                      +   V _

                +        8H               100

100cos(20t) V                 240          500 uF                3sin(20t)
                _




                                                                             4
 Lecture #22        EGR 260 – Circuit Analysis
Mesh equations:
Example: Solve for the voltage V using mesh equations.

                +       10        50 mH             30
                                                                 +
50cos(400t) V
                                     100 uF              50 uF   V
                _
                                                                 _




                                                                     5
Lecture #22      EGR 260 – Circuit Analysis
Node equations:
Example: Solve for the current i(t) using node equations.

                            1 F               6
                  +         8
3sin(4t)         V1    4                           +   V1
                                  i(t)   2H        _
                  _                                     2




                                                            6
Lecture #22          EGR 260 – Circuit Analysis
Superposition:
Superposition can be used to analyze multiple-source AC circuits in a manner very
similar to analyzing DC circuits. However, there are two special cases where it is
highly recommended that superposition be used:
• Circuits that include sources at two or more different frequencies
• Circuits that include both DC and AC sources (Note: you could think of DC
  sources as acting like AC sources with w = 0.)
Example 1 (sources with different frequencies): Solve for the voltage V using superposition.
                 +     V   _


             +         4                            +
                                         1 F
                                         8
2cos(4t) V                     4                        3cos(2t) V
             _                                      _




                                                                                      7
 Lecture #22      EGR 260 – Circuit Analysis
 Example 2 (AC and DC sources): Solve for the voltage V using superposition.
                 +   V   _


             +       2                  3        0.8 H
                                                            +
6cos(5t) V                      0.2 F                       _   10 V
             _




                                                                               8
 a function with 5 inputs.
      X X X X X
       5 4 3 2 1   Y
      0 0 0 0 0    0
      0 0 0 0 1    1
      0 0 0 1 0    0
      0 0 0 1 1    0
      0 0 1 0 0    1
      0 0 1 0 1    1
      0 0 1 1 0    0
      0 0 1 1 1    0             LUT
      0 1 0 0 0    1
      0 1 0 0 1    0
      0 1 0 1 0    0
      0 1 0 1 1    1                                    OUT
      0 1 1 0 0    1
      0 1 1 0 1    1
      0 1 1 1 0    1
      0 1 1 1 1    1
      1 0 0 0 0    0
      1 0 0 0 1    0
      1 0 0 1 0    0
      1 0 0 1 1    0
      1 0 1 0 0    0
      1 0 1 0 1    0
      1 0 1 1 0    0
      1 0 1 1 1    1
      1 1 0 0 0    0             LUT
      1 1 0 0 1    1
      1 1 0 1 0    0
      1 1 0 1 1    1
      1 1 1 0 0    0
      1 1 1 0 1    1
      1 1 1 1 0    0                                                   8
      1 1 1 1 1    0
 Lecture #10 EGR 270 – Fundamentals of Computer Engineering
Other FPGA features
FPGAs also contain a number of other features including:
• Dedicated paths to allow for fast carries in addition
• Multipliers
• Embedded microprocessors - System on a Chip (SoC)
• Blocks of RAM (embedded memory)
• Some newer FPGAs use 6-input LUTs

Another difference between PLDs and FPGAs
• Note that PLDs are EEPROM based so that downloaded designs are not lost
  when the device is powered down.
• On the other hand, most FPGAs are SRAM-based (LUTs are small SRAMs).
  Therefore if you download a design into an FPGA and then power down the
  device, the design is lost. However, FPGAs often include separate
  EEPROM which can be used to reload the design when the device is
  powered up. We will see this in lab.
                                                                    9
     Lecture #10 EGR 270 – Fundamentals of Computer Engineering
     FPGA applications
      - Automotive Under-the-Hood Electronics
      - Automotive Entertainment Systems
      - Cellphones & Communicators
      - Customer Premises Equipment
      - Wired Communications Infrastructure
      - Wireless Communications Infrastructure
      - Compute Platforms
      - HDDs & Storage Systems
      - Office Equipment & Computer Peripherals
      - Wired Games Consoles
      - Handheld Games Consoles
      - Media Players/MP3 Players
      - Cameras & Camcorders
      - TVs & Set-top Boxes
      - DVD Recorders & Players
      - Other Consumer Electronics
      - Industrial Automation & Drives
      - Medical Electronics
      - Chip Cards & Payment Processing
      - Other Industrial Electronics
10
      - Military/Aerospace           http://www.researchandmarkets.com/reports/836306
FGPA Applications




                                            11
    SMT387-VP20-6 Disk Storage Controller
FGPA Applications




                                        12
  Data Acquisition and Playback board
Lecture #10 EGR 270 – Fundamentals of Computer Engineering
FPGAs versus ASICs
FPGAs are user-programmed devices and are often sufficient for small volume
projects. As volume increases, designs can be sent to semiconductor manufacturers to
fabricate custom devices, or Application Specific Integrated Circuits (ASICs).


 ASICs                                       FPGAs
 • High performance                          • Use off-the-shelf devices
 • Low power                                 • Short time to market
 • Lower cost for high volume                • Easily modified
   (perhaps > 250,000 devices)               • Low development cost
 • More efficient routing                    • Cost effective for low volume
 • Long lead time needed for time-             (perhaps < 250,000 devices)
   consuming fabrication at                  • Routing limitations may limit size
   manufacturing facility                      of design (perhaps only half of the
 • Design changes very expensive               available gates can be effectively
                                               used)


                                                                               13
Lecture #10 EGR 270 – Fundamentals of Computer Engineering
FPGAs versus ASICs


Gartner: ASIC design starts to fall by
22% in '09
Dylan McGrath
EE Times
(03/30/2009)

SAN FRANCISCO—FPGAs are
displacing ASICs—a trend that in 2009
will be exacerbated by the global
financial crisis—and now have a 30-to-
one edge in design starts, according to
market research firm Gartner Inc. ASIC
design starts are expected to drop by 22
percent in 2009 as the economy causes
firms to push out and—in some cases—
cancel designs, Gartner (Stamford,
Conn.) said.
                                                             14
Lecture #10   EGR 270 – Fundamentals of Computer Engineering
Major FPGA manufacturers
 SRAM-based FPGAs
 Xilinx, Inc.                         Xilinx and Altera represent about
 Altera Corp.                         60% of the FPGA market
 Atmel
 Lattice Semiconductor

  Flash & antifuse FPGAs
  Actel Corp.
  Quick Logic Corp.
Notes:
• Volatile memory, including SRAM and DRAM, loses its information when
  powered down.
• Non-volatile memory, including flash memory, does not lose its power
  when powered down.
• Most FPGAs are currently SRAM-based. They are easier to manufacture, as
  well as denser (40 nm versus 150 nm) and cheaper.                 15
     Lecture #10   EGR 270 – Fundamentals of Computer Engineering
     Xilinx FPGAs
     Old families
         XC3000, XC4000, XC5200 (old 0.5µm, 0.35µm and 0.25µm technology)
     High-performance families
         Virtex (0.22µm), Virtex-E, Virtex-EM (0.18µm)
         Virtex-II, Virtex-II PRO (0.13µm)
         Virtex-4 (90 nm)
         Virtex-5 (65 nm)
         Virtex-6 (40 nm)
         EasyPath-6 (lower cost version based on Virtex-6 design)
     Low Cost Family
        Spartan/XL, Spartan-IIE
        Spartan-3E (90 nm, 100k – 1.5M gates)
            Note: We will use the Spartan-3E with 100k gates in lab
        Extended Spartan 3A (90 nm, 50k – 3.4M gates)
        Spartan-6 (45 nm)
16
     What’s next? Xilinx and Altera are working on 28 nm technology FPGAs
Lecture #10   EGR 270 – Fundamentals of Computer Engineering
Spartan-3E FPGA Specifications




                           Spartan-3E XC3S100E is used in lab
Other Xilinx FPGAs




                                                                17
      Lecture #10 EGR 270 – Fundamentals of Computer Engineering
     Spartan-3E FPGA Development Boards
     It is common to use development boards to test your designs. The board provides easy
     access to I/Os, ports (USB, video, etc). Once a design has been developed, the FPGA may
     be placed on a custom board within the desired commercial application.




        Spartan-3E Eval Board                Digilent BASYS2 FPGA Board (100k or 250k)




18                                           Digilent NEXYS2 FPGA Board (500k gates)
           Spartan-3E Starter Kit
Lecture #10 EGR 270 – Fundamentals of Computer Engineering
Digilent BASYS2 FPGA Board
Digilent is a company that makes FPGA boards for educational use. The BASYS2
board uses the Xilinx Spartan-3E FPGA and is available with either 100k gates ($59) or
250k gates ($79). Digilent also produces the NEXYS2 board which uses the Xilinx
Spartan-3E FPGA with 500k gates ($99).
We will use the BASYS2 board in lab. Our BASYS2 features:
• 100 k gates
• 1920 LUTs (slices)
• 8 slide switches for inputs
• 4 pushbutton switches for inputs
• 8 LEDs for outputs
• Four 7-segment displays for outputs
• USB2 port, VGA port, and PS2 port
• Multiple clock sources (1 Hz, 25 MHz, 50 MHz, 100 MHz)
• FPGA board can be powered through the USBs connection or separately
• Four 6-pin Pmod (peripheral module) connectors for external circuitry and devices
• Flash ROM to store programmed connections
• 72k Block RAM, 15k Distributed RAM
                                                                                19
• 4 dedicated multipliers
Digilent BASYS2 FPGA Board

         8 LEDs                                              Jumper JP3
                         Four 6-pin Pmod connectors
                                                             (PC or ROM
                                                               mode)
 PS2 Port
(keyboard)




                                                                  VGA
USB2                                                              Port
                                                                 (video)


                                                                 Four
Power
                                                              7-segment
Switch
                                                               displays



                     8 slide switches        4 push-button
                                                                  20
                                                switches
Digilent BASYS2 Board

Pinout – The pinout shown includes
pin numbers (G12, C11, etc) for the
input switches and the output LEDs
and 7-segment displays.
LEDs: active-HIGH (light when output is
HIGH)
Button Switches: produce a HIGH input
when pressed
7-segment Displays: common-anode
displays, so a LOW on CA turns on
segment a. Note that all like segments are
tied together on the 4 displays. To turn on a
display, it must be enabled (or ―asserted‖)
using AN0 – AN3 (active-LOW). So if
AN0 is LOW, then display 0 is enabled. If
AN3 is HIGH, then display 3 is disabled.
To use more than one display at a time, they
must be multiplexed (the human eye can’t
tell if each display is actually ON for only
¼ of the time if multiplexed at a 60 Hz
rate).                                       21
Digilent BASYS2 FPGA Board
The Spartan-3E is available in different packages. The CP132 package is used on the BASYS2
board. In the CP132 package 132 pins are arranged in columns (1-14) and rows (A-P) as shown
below.
                                                                          Legend




22
Digilent BASYS2 FPGA Board

Full pinout




                             23
How do we program an FPGA? - 3 steps:
                       HDL Programming Tool
  •   FPGAs are programmed in VHDL or Verilog
  •   Programs could be used with any FPGA
  •   Dominant VHDL software: Aldec Active-HDL and ModelSim
  •   Others: Xilinx ISE, Quartus II, BlueHDL, VHDL Simili, ….


                              Synthesis Tool
 •    Used to implement or “synthesize” the VHDL design into a specific FPGA
 •    Synopsis Synplify – works with various manufacturer’s FPGAs
 •    Xilinx ISE for Xilinx FPGAs
 •    Quartus II for Altera FPGAs
 •    ispLever for Lattice FPGAs (or Synopsis Synplify Lattice Edition)

                                Downloader
 • Used to download the design into a specific FPGA board
 • Example: Digilent Adept is used for the Digilent BASYS2 FPGA Board
                                                                   24
What specific software will we use in lab to program an FPGA?
     Aldec Active-HDL 8.1
        Describe circuit design
             using VHDL

                    vhd file (e.g., MyFile.vhd)


          Xilinx ISE 11
     Synthesize design for Xilinx
         Spartan-3E FPGA

                     bit file (e.g., MyFile.bit)


         Digilent Adept
Download to specific FPGA board:
                                            USB2
Digilent BASYS2 with Spartan-3E
                                            cable
25
                                                    Digilent BASYS2 FPGA Board
Lecture #10     EGR 270 – Fundamentals of Computer Engineering
Hardware Description Language (HDL)
• Until the 1980’s schematics were the primary means for describing digital
  circuits and systems. Hardware description languages (HDLs) were
  introduced in the 1980 for specifying logic equations to be used in PLDs.
• In the 1990’s the use of PLDs, CPLDs, and FPGAs grew as the devices
  became inexpensive and denser (containing a larger number of equivalent
  gates).
• It has become increasingly difficult to describe large digital circuits and
  systems with schematics alone and now HDL’s have become the primary
  tool for digital designer to design large digital systems. HDL’s can be used
  to describe both top-level and detailed module-level digital systems.
• Computer programmers typically use high-level languages like C++ or Java
  so that they can deal with larger, more complex programs compared working
  with detailed assembly language programs. In a similar manner, HDL’s
  allow digital designers to describe large, complex systems without working
  at the detailed schematic level.

                                                                        26
Lecture #10     EGR 270 – Fundamentals of Computer Engineering
Hardware Description Language (HDL)
There are two primary Hardware Description Languages:
1. VHDL (Very High-Speed Integrated Circuit HDL)
2. Verilog HDL

VHDL and Verilog are like C++ and other high level languages in that they:
• Support modular and hierarchical coding
• Support a variety of high-level constructs, including arrays, procedure and
  function calls, conditional statements, and iterative statements

VHDL and Verilog are different from high level languages in that they:
• Are well-suited to work with potentially millions of signals that can be
  changing concurrently.
• Support a number of signals, devices, and other features related to digital
  hardware components.

                                                                          27
 Lecture #10 EGR 270 – Fundamentals of Computer Engineering
VHDL
• Developed by the Dept. of Defense and IEEE in the 1980’s.
• Was first standardized by IEEE-1076 in 1987 (VHDL-1987)
• Was extended in 1993 (VHDL-1993) and in 2002 (VHDL-2002)

Verilog HDL
• Developed by Gateway Design Automation in 1984 as a proprietary HDL.
• Gateway Design Automation was acquired by Cadence Design Systems in
   1989
• Was first standardized by IEEE-1364 in 1993 (Verilog-1995)
• Was updated in 2001 (Verilog-2001)

Notes:
• The use of each HDL is currently about 50/50.
• VHDL and Verilog are similar enough that if you learn one HDL you can
  easily transition to the other.
• The Aldec Active-HDL software used in lab supports both languages. 28
• We will only use VHDL.
      Lecture #10 EGR 270 – Fundamentals of Computer Engineering
     IEEE1164
     • IEEE1164 is a standard that is not part of VHDL, but is almost always used
        with VHDL. Essentially all vendors support IEEE1164.
     • Including IEEE1164 in VHDL is similar to including libraries in C++
        programs.                                        Logic Value   Interpretation
     • As an example, a VHDL file might begin with:
                                                                U        Uninitialized
              library ieee;
                                                                X        Forcing unknown
              use ieee.std_logic_1164.all;
     IEEE1164 features
                                                                0        Forcing 0
     • Defines basic logic operations such as not,
       and, or, nor, nand, xor, and xnor.                       1        Forcing 1

     • Defines a nine-valued logic system (see                  Z        High impedance
       table) and rules for how to interpret them.
                                                               W         Weak unknown
       For example, what happens if a signal is
       concurrently set to both a 0 and 1 value (a              L        Weak 0
       design error)? Its value is denoted by X.
                                                               H         Weak 1
       What happens if a signal is given no initial
29
       value? Its value if denoted by U.                        -        Don’t care
 Lecture #10 EGR 270 – Fundamentals of Computer Engineering
VHDL Program Structure
The key idea in VHDL programs is to create and define a hardware module while
hiding its internal details. This is done by defining two key parts to a program:
1) The entity – this is simply a description of the module’s inputs and outputs.
   The entity essentially describes a ―black box‖ without defining how it works.
2) The architecture – this is a detailed description of the module’s internal
   behavior or structure. Note that each statement in the architecture is executed
   concurrently, not sequentially (this is quite different from other
   programming languages).




                                                                          30
Lecture #10          EGR 270 – Fundamentals of Computer Engineering
Example: Entity and architecture for a 2-input AND gate
The VHDL instructions for defining the entity and architecture are illustrated below
with a simple example: implementing a 2-input AND gate
     Entity (named AND_gate)
                                     library IEEE;
A
                                     use IEEE.STD_LOGIC_1164.all;
                            F
 B                                   Entity AND_gate is
                                              port
                                              (
                                                       A: in std_logic;
                                                       B: in std_logic;
                                                       F: out std_logic
A
                                              );
           F <= A and B     F        end AND_gate;
 B
                                     Architecture AND_behavior of AND_gate is
                                              begin
                                                     F <= A and B;
     Add the architecture (named              end AND_behavior ;
     AND_behavior) to the entity                                                31
Lecture #10       EGR 270 – Fundamentals of Computer Engineering
Testbench
We test the proper operation of a digital design through simulation. In VHDL this is done
by creating a testbench.
In the testbench we provide a stimulus (input waveforms, for example) and specify the
observed output (output waveforms or truth table).
Many VHDL software packages include a testbench generator which sets of much of the
structure of the testbench. The programmer then needs to specify the input waveforms.




                                                                                32
Lecture #10         EGR 270 – Fundamentals of Computer Engineering
Example: Testbench for the previous VHDL definition of a 2-input AND gate module
The testbench generator will        entity and_gate_tb is
produce the testbench file to the   end and_gate_tb;
right. The user needs to specify
                                    architecture TB_ARCHITECTURE of and_gate_tb is
the stimulus (input waveforms)
                                                 -- Component declaration of the tested unit
in the location indicated below.
                                                 component and_gate
                                                               port( A : in std_logic; B : in std_logic; F :
Note that to test a 2-input AND     out std_logic );
gate with inputs A and B, we can                 end component;
                                                 -- Stimulus signals - signals mapped to the input and
use the waveforms below to test
                                    inout ports of tested entity
the 4 possible combinations of A                 signal A : std_logic;
and B:                                           signal B : std_logic;
                                                 -- Observed signals - signals mapped to the output
  A                                 ports of tested entity
                                                 signal F : std_logic;
                                    begin
  B                                              -- Unit Under Test port map
                                                 UUT : and_gate
      0     1   2    3                                         port map ( A => A, B => B, F => F);


          Add stimulus here                  -- Add your stimulus here ...                       33
                                    end TB_ARCHITECTURE;
Lecture #10          EGR 270 – Fundamentals of Computer Engineering
Stimulus                           entity and_gate_tb is
                                   end and_gate_tb;
The waveforms for A and B just
shown will yield the 4 possible
                                   architecture TB_ARCHITECTURE of and_gate_tb is
combinations of A and B, but we                 -- Component declaration of the tested unit
will also need to specify the                   component and_gate
time increments for each                                      port( A : in std_logic; B : in std_logic; F :
waveform. If each input            out std_logic );
combination last for 10 ns, then                end component;
the waveforms relate to time as                 -- Stimulus signals - signals mapped to the input and
                                   inout ports of tested entity
shown below:
                                                signal A : std_logic;
                                                signal B : std_logic;
  A
                                                -- Observed signals - signals mapped to the output
                                   ports of tested entity
 B                                              signal F : std_logic;
                                   begin
                                                -- Unit Under Test port map
      0    10   20   30                         UUT : and_gate
      ns   ns   ns   ns
                                                              port map ( A => A, B => B, F => F);
                                                -- Add your stimulus here ...
Stimulus instructions here
                                                 A <= '0', '1' after 20 ns;
describe the waveforms A
                                                 B <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
and B above.                       end TB_ARCHITECTURE;
                                                                                                  34
Lecture #10     EGR 270 – Fundamentals of Computer Engineering
Simulation Results
The VHDL files just described were simulated using Aldec Active-HDL. This software
can display the results either in the form of a truth table or as waveforms. They are
shown in the form of a truth table below.




                                                                              35
Lecture #10      EGR 270 – Fundamentals of Computer Engineering
More details on VHDL
• VHDL is not case-sensitive.
• VHDL ignores spaces and line breaks.
• Comments are indicated to two consecutive dashes ―- -‖ (see examples below).
• VHDL has reserved words including entity, architecture, in, out, inout, port, begin,
  end, when, else, not, and, or, nand, nor, xor, xnor, and others.
• Signal names in VHDL may use letters, numbers, and underscores.
• Signal types (directions) may be in, out, inout, or buffer.
    - - Sample program for EGR 270
    Entity mymodule is
       port
       (        A,B,C,D: in std_logic;
                F: out std_logic;
                G: inout std logic); - - Note that G can be an input or an output
    end mymodule;


• The assignment operator <= is used to assign value to signals.
• No precedence is used in VHDL so use parentheses liberally. For example,
  if F = A’B + BC’, this expression might be assigned to F as follows:
                                                                                36
        F <= ((not A) and B) or (B and (not C));
 Lecture #10      EGR 270 – Fundamentals of Computer Engineering

Modeling styles within an architecture
VHDL architectures may be described in three manners:
1. Structural description
    • Description is based on interconnection of components (to be introduced shortly).
      Similar to a schematic. We might define components for gates, decoders, adders, etc.,
      and then describe how they are connected.
    • Works well for simple circuits, but not for huge designs
    • Is closely related to the hardware in which it will be implemented, so the design is
      relatively straightforward and easily implemented by the software.
2. Dataflow description
    • Outputs are described using signal assignments without specifying the underlying
      hardware.
    • Example: f<= ((not A) and B) or (C and D);
3. Behavioral description
    • Describes what the system or circuit does, rather than describing the components.
    • Typically involves the uses of processes.
    • Allows for the use of more abstract constructs (functions, conditional and iterative
      structures, etc.)
    • More powerful for large designs, but requires experience to avoid unrealistic designs.
                                                                                   37
Lecture #10 EGR 270 – Fundamentals of Computer Engineering
Example: Design and Test a Gray Code to Binary Converter

Procedure:
1) Develop set of equations
    • Truth table
    • K-maps
    • Equations
2) Develop a VHDL structural description of the solution
3) Test the solution by simulation



Illustration:


                G3             Gray Code                   B3
                G2             to Binary                   B2
                G1             Converter                   B1
                G0                                         B0
                                                                38
Lecture #10     EGR 270 – Fundamentals of Computer Engineering
                             Gray Code              Binary
Truth Table:
Gray Code to           G3    G2    G1    G0   B3   B2    B1      B0
Binary Converter        0    0      0    0    0    0     0       0
                        0    0      0    1    0    0     0       1
                        0    0      1    0    0    0     1       1
                        0    0      1    1    0    0     1       0
                        0    1      0    0    0    1     1       1
                        0    1      0    1    0    1     1       0
                        0    1      1    0    0    1     0       0
                        0    1      1    1    0    1     0       1
                        1    0      0    0    1    1     1       1
(Note that G3 = B3)     1    0      0    1    1    1     1       0
                        1    0      1    0    1    1     0       0
                        1    0      1    1    1    1     0       1
                        1    1      0    0    1    0     0       0
                        1    1      0    1    1    0     0       1
                        1    1      1    0    1    0     1       1
                        1    1      1    1    1    0     1       0    39
     Lecture #10         EGR 270 – Fundamentals of Computer Engineering
  K-Maps: Gray Code to Binary Converter
    G1G0                              G1G0                           G1G0
G3G2   00      01   11    10   G3G2        00   01   11   10     G3G2   00    01   11   10

    00     0   0    0      0          00   0    0    1     1         00   0   1    0    1

    01     1   1    1      1          01   1    1    0     0         01   1   0    1    0

     11    0   0    0      0          11   0    0    1     1         11   0   1    0    1

    10     1   1    1      1          10   1    1    0     0         10   1   0    1    0

          B2  G3  G2                 B1  G3  G2  G1           B0  G3  G2  G1  G0
  Equations: The equations from the K-maps can be re-expressed as follows:
  B3  G3                                                      B3  G3
  B2  G3  G2                                                 B2  G3  G2
  B1  G3  G2  G1                                            B1  B2  G1
                                                                                   40
  B0  G3  G2  G1  G0                                       B0  B1  G0
 Lecture #10     EGR 270 – Fundamentals of Computer Engineering
Schematic: Gray Code to Binary Converter


   G3                                                             B3


                                                                  B2
   G2



                                                                  B1
   G1



                                                                  B0
   G0




                                                                   41
Lecture #10     EGR 270 – Fundamentals of Computer Engineering
VHDL Code: Entity and Architecture for Gray Code to Binary Converter
   library IEEE;
   use IEEE.STD_LOGIC_1164.all;
   entity Gray2Binary is
              port(
                       G3,G2,G1,G0 : in STD_LOGIC;
                       B3,B2,B1,B0 : out STD_LOGIC);
   end Gray2Binary;
   architecture Gray2Binary of Gray2Binary is
             signal T2, T1 : STD_LOGIC; - - define intermediate signals
   begin
             T2 <= G3 XOR G2;
             T1 <= T2 XOR G1;
             B3 <= G3;
             B2 <= T2;
             B1 <= T1;
             B0 <= T1 XOR G0;
   end Gray2Binary;                                                       42
Lecture #10      EGR 270 – Fundamentals of Computer Engineering
VHDL Testbench: The stimulus portion of the testbench is shown below. The rest of
the testbench file is created automatically by the testbench generator. Note that the
stimulus will generate waveforms to test all 16 possible input combinations for the
Gray Code to Binary Code Converter.




   -- Add your stimulus here ...
   G0<= '0', '1' after 10ns, '0' after 20ns, '1' after 30ns, '0' after 40ns,
         '1' after 50ns, '0' after 60ns, '1' after 70ns, '0' after 80ns,
         '1' after 90ns, '0' after 100ns, '1' after 110ns, '0' after 120ns,
         '1' after 130ns, '0' after 140ns, '1' after 150ns, '0' after 160ns;
   G1<= '0', '1' after 20ns, '0' after 40ns, '1' after 60ns, '0' after 80ns,
         '1' after 100ns, '0' after 120ns, '1' after 140ns, '0' after 160ns;
   G2<= '0', '1' after 40ns, '0' after 80ns, '1' after 120ns, '0' after 160ns;
   G3<= '0', '1' after 80ns, '0' after 160ns;


                                                                                 43
Lecture #10     EGR 270 – Fundamentals of Computer Engineering
Simulation Results: The results of the simulation using Aldec Active-HDL are shown
below in both truth table form and as waveforms.




                                                                            44
Lecture #10      EGR 270 – Fundamentals of Computer Engineering
VHDL Code – Vector approach: Alternate approach using vectors to store the 4-bit
input and 4-bit output codes for the Gray Code to Binary Code Converter.
-- Gray Code to Binary Code Converter using vectors
-- for the 4-bit input and the 4-bit output
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Gray2BinaryV is
       port(
             G : in STD_LOGIC_VECTOR (3 downto 0); -- define input vector
             B : out STD_LOGIC_VECTOR (3 downto 0) -- define output vector
         );
end Gray2BinaryV;
architecture Gray2BinaryV of Gray2BinaryV is
      signal T2, T1 : STD_LOGIC; -- define intermediate signals
begin
      T2 <= G(3) XOR G(2);
      T1 <= T2 XOR G(1);
      B(3) <= G(3);
      B(2) <= T2;
      B(1) <= T1;
      B(0) <= T1 XOR G(0);
                                                                             45
end Gray2BinaryV;
Lecture #10      EGR 270 – Fundamentals of Computer Engineering
VHDL Testbench – alternate form using vectors: The stimulus portion of the
testbench is shown below. Since G is a 4-valued vector, all 4 values can be assigned at
one time (for each time increment). Note that the stimulus will generate waveforms to
test all 16 possible input combinations for the Gray Code to Binary Code Converter.

   -- Add your stimulus here ...
            G <=     "0000",                         "0001" after 10 ns,
                     "0011" after 20 ns,             "0010" after 30 ns,
                     "0110" after 40 ns,             "0111" after 50 ns,
                     "0101" after 60 ns,             "0100" after 70 ns,
                     "1100" after 80 ns,             "1101" after 90 ns,
                     "1111" after 100 ns,            "1110" after 110 ns,
                     "1010" after 120 ns,            "1011" after 130 ns,
                     "1001" after 140 ns,            "1000" after 150 ns;




                                                                                 46
Lecture #10     EGR 270 – Fundamentals of Computer Engineering
Simulation Results (using vectors): The results of the simulation using Aldec Active-
HDL are shown below as waveforms (also shown in hexadecimal form).




                                                                              47
Lecture #10    EGR 270 – Fundamentals of Computer Engineering
References:
• BASYS2 Reference Manual – www.digilentinc.com
• ECE 448 – FPGA and ASIC Design with VHDL presentation, George Mason
  University
• Xilinx Spartan-3E FPGA Data Sheet – www.xilinx.com




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