Digital Temperature Controller - PowerPoint by hcj

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									   Sponsored by Phonon Corp
Advisor: Professor Tehranipoor

         Colin Gladding (EE)
       Harpreet Mankoo (EE)
            Joe Mascola (EE)
             Dave Sidoti (EE)
•Review
•Research / Design
•Future Objectives
•Budget and scheduling
•Conclusion/Questions
Design Review
 Design/implement the third
  generation temperature controller
  for military SAW applications

 Temperature Range: -55 to 125 °C

 Control loop
    PID Controller
    Feedback from thermistor
    PWM from output

 User configuration
  using a bidirectional voltage regulator on the powerline

 Externally accessible memory
•Review
•Research/Design
•Future Objectives
•Budget and scheduling
•Conclusion/Questions
Research and Development
 Team member responsibilities

   Colin Gladding: Control system and PID tuning


   Harpreet Mankoo: coding and software


   Joe Mascola: interfacing microcontroller with analog
    thermistor and syncing with input
R&D: PWM
 General aim to familiarize us
 with new dsPIC
   Necessary software installed,
    specific board selected

 Implemented a working code
    Controls LED intensity via
     potentiometer
 Results:




             dsPIC30F2020
                               ~10% duty cycle




             ~25% duty cycle       ~80% duty cycle
R&D Thermistor and A/D
Conversion
 Read in an analog voltage value from thermistor
    Looking into:




 Perform an A/D conversion
    Thermistor voltage value input into the PID
R&D Thermistor
 Nonlinear relationship between temperature and
 resistance
   Equation relates temperature to resistance/voltage
   Specialized to the specific thermistor we choose
   Waiting for Phonon on this
R&D: Control Loop

Temp Setpoint                        Digital PWM
                     PI Controller
  Ki Kp freq                           Output




                Current Temp         MOSFET and
                   Sensor              heater
R&D: PID Controller
 Configured within the microcontroller
    Has to be tuned for optimum efficiency
       Professor Pattipatti also helped us along with this research


   Output of PID configures the duty cycle of each period
       The exact algorithm we will implement is up to us as designers
         Ratio of the output value to the percentage of period being
          used
•Review
•Research / Design
•Future Objectives
•Budget and scheduling
•Conclusion/Questions
Future Objectives: Bidirectional
Configuration


          BI DIRECTIONAL         VDD
          VOLTAGE REGULATOR

 +Vdd     IN          OUT     UART

                GND

 Logic
Future Objectives: Memory
 Microcontroller has extra memory
  available
   May not be enough


 Using an external memory chip
  may be easier in the long run

 Would store:
   System parameters
   Setpoints
   Optional customer-defined data
•Review
•Research / Design
•Future Objectives
•Budget and Scheduling
•Conclusion/Questions
       Budget:
             Unchanged Since Last Time
ITEM   QTY                 DESCRIPTION                             UNIT PRICE   SUBTOTAL

   1    5          88K3883 MICROCHIP DSPIC30F2020-30I/SP             $5.81       $29.05



   2    1      16M5244 MICROCHIP AC244002 High Speed Driver         $159.98      $159.98



   3    1      16M6059 MICROCHIP DV244005 ICE and STD Driver        $499.98      $499.98

   4    1          92C5431 MICROCHIP SW006012 C-Compiler            $895.00      $895.00



   5    1     98M0791 MICROCHIP DV243003 I2C Serial Read / Write     $79.98      $79.98



   6    2      26M9183 MICROCHIP DM300023 SMPS Demo Board           $149.99      $299.98



   7    2      39M8082 MICROCHIP DM300027 28-Pin Demo Board          $79.99      $159.98

   8   10          62K0579 MICROCHIP 24LC16B-I/P Memory              $0.32        $3.20

   9   10          38C8727 Molex multipole connector female          $0.19        $1.89

  10   10           97B2624 Molex multipole connector male           $0.18        $1.78
                                                                    Total
                                                                                $2,130.82
   Timeline:
             So far right on schedule
               SEP OCT NOV DEC JAN FEB MAR APR MAY

 Research/
 Planning
 Prototype
  Design

 Integrate
  Design
  System
  Testing
    Final
Deliverables

								
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