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Verilog Coding Guidelines

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					                   Verilog Coding Guidelines *


Guideline 1:
When modeling sequential logic, use non-blocking assignments.
Guideline 2:
When modeling latches, use non-blocking assignments.
Guideline 3:
When modeling combinational logic with an always block, use blocking
assignments.
Guideline 4:
When modeling both sequential and combinational logic within the same
always block, use non-blocking assignments.
Guideline 5:
Do not mix blocking and non-blocking assignments in the same always
block.
Guideline 6:
Do not make assignments to the same variable from more than one
always block.
Guideline 7:
Use $strobe to display values that have been assigned using non-blocking
assignments.
Guideline 8:
Do not make assignments using #0 delays.


*Suggested by Cliff Cummings “Non-blocking Assignments in Verilog
Synthesis, Coding Styles That Kill!” SNUG 2000

				
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Description: Verilog HDL is the most widely used hardware description language. Verilog HDL can be used for a variety of levels of logic design, digital system can also be logic synthesis, simulation and timing analysis.