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COMP427 Embedded Systems Lecture 4. ARM Instructions ARM Instruction Overview • ARM is a RISC machine, so the instruction length is fixed In the ARM mode, the instructions are 32-bit wide In the Thumb mode, the instructions are 16-bit wide • Most ARM instructions can be conditionally executed It means that they have their normal effect only if the N (Negative), Z (Zero), C (Carry) and V (Overflow) flags in the CPSR satisfy a condition specified in the instruction • If the flags do not satisfy this condition, the instruction acts as a NOP (No Operation) • In other words, the instruction has no effect and advances to the next instruction 2 Korea Univ ARM Instruction Format Arithmetic and Logical Instructions Memory Access Instructions (Load/Store) Branch Instructions Software Interrupt Instruction 3 Korea Univ Condition Field 4 Korea Univ Flags Which flags would you check? (N, Z, C, V) Unsigned higher ua > ub ? C=1 Unsigned lower ua < ub ? C=0 Signed greater than sa > sb ? Signed less than sa < sb ? Signed greater than Signed less than sa > sb? Yes if (N == V) sa < sb? Yes if (N != V) (+) - (+) : N=0 & V=0 (+) - (+) : N=1 & V=0 (+) - (-) : N=0 & V=0 or (+) - (-) : N=0 & V=0 or : N=1 & V=1 : N=1 & V=1 (-) - (+) : N=1 & V=0 or (-) - (+) : N=1 & V=0 or : N=0 & V=1 : N=0 & V=1 (-) - (-) : N=0 & V=0 (-) - (-) : N=1 & V=0 5 Korea Univ Data Processing Instructions • Move instructions • Arithmetic instructions • Logical instructions • Comparison instructions • Multiply instructions 6 Korea Univ Execution Unit in ARM Rn Rm No pre-processing Barrel Shifter Pre-processing N ALU Rd 7 Korea Univ Move Instructions Rn Rm Barrel Shifter Syntax: <instruction>{cond}{S} Rd, N N MOV Move a 32-bit value into a register Rd = N MVN Move the NOT of the 32-bit value into a register Rd = ~ N ALU Rd 8 Korea Univ Move Instructions – MOV • MOV loads a value into the destination register (Rd) from another register, a shifted register, or an immediate value Useful to setting initial values and transferring data between registers It updates the carry flag (C), negative flag (N), and zero flag (Z) if S bit is set • C is set from the result of the barrel shifter MOV R0, R0; move R0 to R0, Thus, no effect MOV R0, R0, LSL#3 ; R0 = R0 * 8 MOV PC, R14; (R14: link register) Used to return to caller MOVS PC, R14; PC <- R14 (lr), CPSR <- SPSR ; Used to return from interrupt or exception * SBZ: should be zeros 9 Korea Univ MOV Example Before: cpsr = nzcv r0 = 0x0000_0000 r1 = 0x8000_0004 MOVS r0, r1, LSL #1 After: cpsr = nzCv r0 = 0x0000_0008 r1 = 0x8000_0004 10 Korea Univ Rm with Barrel Shifter Encoded here MOVS r0, r1, LSL #1 Shift Operation (for Rm) Syntax Immediate #immediate Register Rm Logical shift left by immediate Rm, LSL #shift_imm Logical shift left by register Rm, LSL Rs LSL: Logical Shift Left Logical shift right by immediate Rm, LSR #shift_imm LSR: Logical Shift Right Logical shift right by register Rm, LSR Rs ASR: Arithmetic Shift Right Arithmetic shift right by ROR: Rotate Right Rm, ASR #shift_imm immediate RRX: Rotate Right with Extend Arithmetic shift right by register Rm, ASR Rs Rotate right by immediate Rm, ROR #shift_imm Rotate right by register Rm, ROR Rs Rotate right with extend Rm, RRX 11 Korea Univ Arithmetic Instructions Rn Rm Syntax: <instruction>{cond}{S} Rd, Rn, N ADC add two 32-bit values with carry Rd = Rn + N + carry Barrel Shifter ADD add two 32-bit values Rd = Rn + N N RSB reverse subtract of two 32-bit values Rd = N - Rn reverse subtract of two 32-bit values ALU RSC with carry Rd = N – Rn - !C SBC subtract two 32-bit values with carry Rd = Rn - N - !C SUB subtract two 32-bit values Rd = Rn - N Rd 12 Korea Univ Arithmetic Instructions – ADD • ADD adds two operands, placing the result in Rd Use S suffix to update conditional field The addition may be performed on signed or unsigned numbers ADD R0, R1, R2 ; R0 = R1 + R2 ADD R0, R1, #256 ; R0 = R1 + 256 ADDS R0, R2, R3,LSL#1 ; R0 = R2 + (R3 << 1) and update flags 13 Korea Univ Arithmetic Instructions – ADC • ADC adds two operands with a carry bit, placing the result in Rd It uses a carry bit, so can add numbers larger than 32 bits Use S suffix to update conditional field <64-bit addition> 64 bit 1st operand: R4 and R5 64 bit 2nd operand: R8 and R9 64 bit result: R0 and R1 ADDS R0, R4, R8 ; R0 = R4 + R8 and set carry accordingly ADCS R1, R5, R9 ; R1 = R5 + R9 + (Carry flag) 14 Korea Univ Arithmetic Instructions – SUB • SUB subtracts operand 2 from operand 1, placing the result in Rd Use S suffix to update conditional field The subtraction may be performed on signed or unsigned numbers SUB R0, R1, R2 ; R0 = R1 - R2 SUB R0, R1, #256 ; R0 = R1 - 256 SUBS R0, R2, R3,LSL#1 ; R0 = R2 - (R3 << 1) and update flags 15 Korea Univ Arithmetic Instructions – SBC • SBC subtracts operand 2 from operand 1 with the carry flag, placing the result in Rd It uses a carry bit, so can subtract numbers larger than 32 bits. Use S suffix to update conditional field <64-bit Subtraction> 64 bit 1st operand: R4 and R5 64 bit 2nd operand: R8 and R9 64 bit result: R0 and R1 SUBS R0, R4, R8 ; R0 = R4 – R8 SBC R1, R5, R9 ; R1 = R5 – R9 - !(carry flag) 16 Korea Univ Examples Before: Before: Before: r0 = 0x0000_0000 r0 = 0x0000_0000 r0 = 0x0000_0000 r1 = 0x0000_0002 r1 = 0x0000_0005 r1 = 0x0000_0077 r2 = 0x0000_0001 RSB r0, r1, #0 SUB r0, r1, r2 ADD r0, r1, r1, LSL#1 // r0 = 0x0 – r1 After: After: After: r0 = 0x0000_0001 r0 = 0xFFFF_FF89 r0 = 0x0000_000F r1 = 0x0000_0002 r1 = 0x0000_0077 r1 = 0x0000_0005 r2 = 0x0000_0001 17 Korea Univ Examples Before: cpsr = nzcv r1 = 0x0000_0001 SUBS r1, r1, #1 After: cpsr = nZCv r1 = 0x0000_0000 • Why is the C flag set (C = 1)? 18 Korea Univ Logical Instructions Rn Rm Syntax: <instruction>{cond}{S} Rd, Rn, N Barrel Shifter AND logical bitwise AND of two 32-bit values Rd = Rn & N N ORR logical bitwise OR of two 32-bit values Rd = Rn | N EOR logical exclusive OR of two 32-bit values Rd = Rn ^ N ALU BIC logical bit clear Rd = Rn & ~N Rd 19 Korea Univ Logical Instructions – AND • AND performs a logical AND between the two operands, placing the result in Rd It is useful for masking the bits AND R0, R0, #3 ; Keep bits zero and one of R0 and discard the rest 20 Korea Univ Logical Instructions – EOR • EOR performs a logical Exclusive OR between the two operands, placing the result in the destination register It is useful for inverting certain bits EOR R0, R0, #3 ; Invert bits zero and one of R0 21 Korea Univ Examples Before: r0 = 0x0000_0000 Before: r1 = 0b1111 r1 = 0x0204_0608 r2 = 0b0101 r2 = 0x1030_5070 BIC r0, r1, r2 ORR r0, r1, r2 After: r0 = 0x1234_5678 After: r0 = 0b1010 22 Korea Univ Comparison Instructions • The comparison instructions update the cpsr flags according to the result, but do not affect other registers Rn Rm • After the bits have been set, the information can be used to change program flow by using Barrel Shifter conditional execution N Syntax: <instruction>{cond}{S} Rn, N ALU CMN compare negated Flags set as a result of Rn + N CMP Compare Flags set as a result of Rn – N test for equality of two 32- TEQ Flags set as a result of Rn ^ N Rd bit values TST test bits of a 32-bit value Flags set as a result of Rn & N 23 Korea Univ Comparison Instructions – CMP • CMP compares two values by subtracting the second operand from the first operand Note that there is no destination register It only update cpsr flags based on the execution result CMP R0, R1; 24 Korea Univ Comparison Instructions – CMN • CMN compares one value with the 2‟s complement of a second value It performs a comparison by adding the 2nd operand to the first operand It is equivalent to subtracting the negative of the 2nd operand from the 1st operand Note that there is no destination register It only update cpsr flags based on the execution result CMN R0, R1; 25 Korea Univ Comparison Instructions – TST • TST tests bits of two 32-bit values by logically ANDing the two operands Note that there is no destination register It only update cpsr flags based on the execution result • TEQ sets flags by logical exclusive ORing the two operands 26 Korea Univ Examples Before: cpsr = nzcv r0 = 4 r9 = 4 CMP r0, r9 After: cpsr = nZCv r0 = 4 r9 = 4 27 Korea Univ Branch Instructions • A branch instruction changes the flow of execution or is used to call a routine The type of instruction allows programs to have subroutines, if- then-else structures, and loops Syntax: B{cond} label BL{cond} label B branch pc = label pc = label BL branch with link lr = address of the next instruction after the BL 28 Korea Univ B, BL • B (branch) and BL (branch with link) are used for conditional or unconditional branch BL is used for the subroutine (procedure, function) call To return from a subroutine, use • MOV PC, R14; (R14: link register) Used to return to caller • Branch target address Sign-extend the 24-bit signed immediate (2‟s complement) to 30-bits Left-shift the result by 2 bits Add it to the current PC (actually, PC+8) Thus, the branch target could be ±32MB away from the current instruction 29 Korea Univ Examples B forward ADD r1, r2, #4 ADD r0, r6, #2 ADD r3, r7, #4 BL my_subroutine forward: CMP r1, #5 SUB r1, r2, #4 MOVEQ r1, #0 ….. My_subroutine: backward: < subroutine code > ADD r1, r2, #4 MOV pc, lr // return from subroutine SUB r1, r2, #4 ADD r4, r6, r7 B backward 30 Korea Univ Memory Access Instructions • Load-Store (memory access) instructions transfer data between memory and CPU registers Single-register transfer Multiple-register transfer Swap instruction 31 Korea Univ Single-Register Transfer LDR Load a word into a register Rd ← mem32[address] STR Store a word from a register to memory Rd → mem32[address] LDRB Load a byte into a register Rd ← mem8[address] STRB Store a byte from a register to memory Rd → mem8[address] LDRH Load a half-word into a register Rd ← mem16[address] STRH Store a half-word into a register Rd → mem16[address] Rd ← SignExtend ( LDRSB Load a signed byte into a register mem8[address]) Rd ← SignExtend ( LDRSH Load a signed half-word into a register mem16[address]) 32 Korea Univ LDR (Load Register) • LDR loads a word from a memory location to a register The memory location is specified in a very flexible manner with addressing mode // Assume R1 = 0x0000_2000 LDR R0, [R1] // R0 ← [R1] LDR R0, [R1, #16] // R0 ← [R1+16]; 0x0000_2010 33 Korea Univ STR (Store Register) • STR stores a word from a register to a memory location The memory location is specified in a very flexible manner with a addressing mode // Assume R1 = 0x0000_2000 STR R0, [R1] // [R1] <- R0 STR R0, [R1, #16] // [R1+16] <- R0 34 Korea Univ Load-Store Addressing Mode Base Address register Indexing Method Data Example updated? Preindex with Mem[base + offset] Yes (Base + offset) LDR r0, [r1, #4]! writeback Preindex Mem[base + offset] No LDR r0, [r1, #4] Postindex Mem[base] Yes (Base + offset) LDR r0, [r1], #4 ! Indicates that the instruction writes the calculated address back to the base address register After: r0 ← mem[0x0009_0004] LDR r0, [r1, #4]! r0 = 0x0202_0202 r1 = 0x0009_0004 Before: r0 = 0x0000_0000 After: r0 ← mem[0x0009_0004] LDR r0, [r1, #4] r0 = 0x0202_0202 r1 = 0x0009_0000 Mem32[0x0009_0000] = 0x01010101 r1 = 0x0009_0000 Mem32[0x0009_0004] = 0x02020202 LDR r0, [r1], #4 After: r0 ← mem[0x0009_0000] r0 = 0x0101_0101 r1 = 0x0009_0004 35 Korea Univ Multiple Register Transfer – LDM, STM Syntax: <LDM/STM>{cond}<addressing mode> Rn{!}, <registers>^ LDM Load multiple registers STM Store multiple registers Addressing Description Start address End address Rn! Mode IA Increment After Rn Rn + 4 x N - 4 Rn + 4 x N IB Increment Before Rn + 4 Rn + 4 x N Rn + 4 x N DA Decrement after Rn – 4 x N + 4 Rn Rn – 4 x N DB Decrement Before Rn – 4 x N Rn – 4 Rn – 4 x N 36 Korea Univ Multiple Register Transfer – LDM, STM • LDM (Load Multiple) loads general-purpose registers from sequential memory locations • STM (Store Multiple) stores general-purpose registers to sequential memory locations 37 Korea Univ LDM, STM - Multiple Data Transfer In multiple data transfer, the register list is given in a curly brackets {} It doesn‟t matter which order you specify the registers in • They are stored from lowest to highest STMFD R13! {R0, R1} // R13 is updated LDMFD R13! {R1, R0} // R13 is updated A useful shorthand is “-” • It specifies the beginning and end of registers STMFD R13!, {R0-R12} // R13 is updated appropriately LDMFD R13!, {R0-R12} // R13 is updated appropriately 38 Korea Univ Examples LDMIA r0!, {r1-r3} Before: After: Mem32[0x80018] = 0x3 Mem32[0x80018] = 0x3 Mem32[0x80014] = 0x2 Mem32[0x80014] = 0x2 Mem32[0x80010] = 0x1 Mem32[0x80010] = 0x1 r0 = 0x0008_0010 r0 = 0x0008_001C r1 = 0x0000_0000 r1 = 0x0000_0001 r2 = 0x0000_0000 r2 = 0x0000_0002 r3 = 0x0000_0000 r3 = 0x0000_0003 39 Korea Univ Stack Operation • Multiple data transfer instructions (LDM and STM) are used to load and store multiple words of data from/to main memory Stack Other Description STMFA STMIB Pre-incremental store • IA: Increment After STMEA STMIA Post-incremental store • IB: Increment Before STMFD STMDB Pre-decremental store • DA: Decrement After STMED STMDA Post-decremental store • DB: Decrement Before • FA: Full Ascending (in stack) LDMED LDMIB Pre-incremental load • FD: Full Descending (in stack) LDMFD LDMIA Post-incremental load • EA: Empty Ascending (in stack) LDMEA LDMDB Pre-decremental load • ED: Empty Descending (in stack) LDMFA LDMDA Post-decremental load 40 Korea Univ SWAP Instruction Syntax: SWP{B}{cond} Rd, Rm, <Rn> tmp = mem32[Rn] SWP Swap a word between memory and a register mem32[Rn] = Rm Rd = tmp tmp = mem8[Rn] SWPB Swap a byte between memory and a register mem8[Rn] = Rm Rd = tmp 41 Korea Univ SWAP Instruction • SWP swaps the contents of memory with the contents of a register It is a special case of a load-store instruction It performs a swap atomically meaning that it does not release the bus unitil it is done with the read and the write It is useful to implement semaphores and mutual exclusion (mutex) in an OS SWP r0, r1, [r2] Before: After: mem32[0x9000] = 0x1234_5678 mem32[0x9000] = 0x1111_2222 r0 = 0x0000_0000 r0 = 0x1234_5678 r1 = 0x1111_2222 r1 = 0x1111_2222 r2 = 0x0000_9000 r2 = 0x0000_9000 42 Korea Univ Semaphore Example Spin: MOV r1, =semaphore; // r1 has an address for semaphore MOV r2, #1 SWP r3, r2, [r1] CMP r3, #1 BEQ spin 43 Korea Univ Miscellaneous but Important Instructions • Software interrupt instruction • Program status register instructions 44 Korea Univ SWI (Software Interrupt) • The SWI instruction incurs a software interrupt It is used by operating systems for system calls 24-bit immediate value is ignored by the ARM processor, but can be used by the SWI exception handler in an operating system to determine what operating system service is being requested Syntax: SWI{cond} SWI_number • lr_svc (r14) = address of instruction following SWI • pc = 0x8 SWI Software interrupt • cpsr mode = SVC • cpsr ‘I bit = 1 (it masks interrupts) • To return from the software interrupt, use • MOVS PC, R14; PC <- R14 (lr), CPSR <- SPSR 45 Korea Univ Example 0x0000_8000 SWI 0x123456 After: Before: cpsr = nzcVqIft_SVC cpsr = nzcVqift_USER spsr = nzcVqift_USER pc = 0x0000_8000 pc = 0x0000_0008 lr = 0x003F_FFF0 lr = 0x0000_8004 r0 = 0x12 r0 = 0x12 SWI handler example SWI_handler: STMFD sp!, {r0-r12, lr} // push registers to stack LDR r10, [lr, #-4] // r10 = swi instruction BIC r10, r10, #0xff000000 // r10 gets swi number BL interrupt_service_routine LDMFD sp!, {r0-r12, pc}^ // return from SWI hander 46 Korea Univ Program status register instructions Syntax: MRS{cond} Rd, <cpsr | spsr> MSR{cond} <cpsr | spsr>_<fields>, Rm MSR{cond} <cpsr | spsr>_<fields>, #immediate MRS Copy program status register to a general-purpose register Rd = psr MSR Copy a general-purpose register to a program status register psr[field] = Rm MSR Copy an immediate value to a program status register psr[field] = immediate * fields can be any combination of control (c), extension (x), status (s), and flags (f) Flags[31:24] Status[23:16] eXtension [15:8] Control [7:0] NZ C V I F T Mode 47 Korea Univ MSR & MRS • MSR: Move the value of a general-purpose register or an immediate constant to the CPSR or SPSR of the current mode MSR CPSR_all, R0 ; Copy R0 into CPSR MSR SPSR_all, R0 ; Copy R0 into SPSR • MRS: Move the value of the CPSR or the SPSR of the current mode into a general-purpose register MRS R0, CPSR_all ; Copy CPSR into R0 MRS R0, SPSR_all ; Copy SPSR into R0 • To change the operating mode, use the following code // Change to the supervisor mode MRS R0,CPSR ; Read CPSR BIC R0,R0,#0x1F ; Remove current mode with bit clear instruction ORR R0,R0,#0x13 ; Substitute to the Supervisor mode MSR CPSR_c,R0 ; Write the result back to CPSR 48 Korea Univ (Assembly) Language • There is no golden way to learn language • You got to use and practice to get used to it 49 Korea Univ Backup Slides 50 Korea Univ Overflow/Underflow • Overflow/Underflow: The answer to an addition or subtraction exceeds the magnitude that can be represented with the allocated number of bits • Overflow/Underflow is a problem in computers because the number of bits to hold a number is fixed For this reason, computers detect and flag the occurrence of an overflow/underflow. • Detection of an overflow/underflow after the addition of two binary numbers depends on whether the numbers are considered to be signed or unsigned 51 Korea Univ Overflow/Underflow in Unsigned Numbers • When two unsigned numbers are added, an overflow is detected from the end carry out of the most significant position If the end carry is „1‟, there is an overflow. • When two unsigned numbers are subtracted, an underflow is detected when the end carry is “0” 52 Korea Univ Subtraction of Unsigned Numbers • Unsigned number is either positive or zero There is no sign bit So, a n-bit can represent numbers from 0 to 2n - 1 • For example, a 4-bit can represent 0 to 15 (=24 – 1) To declare an unsigned number in C language, • unsigned int a; x86 allocates a 32-bit for “unsigned int” • Subtraction of unsigned integers (M, N) M – N in binary can be done as follows: • M + (2n – N) = M – N + 2n • If M ≥ N, the sum produces an end carry, which is 2n Subtraction result is zero or a positive number • If M < N, the sum does not produce an end carry since it is equal to 2n – (N – M) Unsigned Underflow: subtraction result is negative and unsigned number can‟t represent negative numbers 53 Korea Univ Overflow/Underflow in Signed Numbers • With signed numbers, an overflow/underflow can‟t occur for an addition if one number is positive and the other is negative. Adding a positive number to a negative number produces a result whose magnitude is equal to or smaller than the larger of the original numbers • An overflow may occur if two numbers are both positive in addition When x and y both have sign bits of 0 (positive numbers) • If the sum has sign bit of 1, there is an overflow • An underflow may occur if two numbers are both negative in addition When x and y both have sign bits of 1 (negative numbers) • If the sum has sign bit of 0, there is an underflow 54 Korea Univ Overflow/Underflow in Signed Numbers 8-bit Signed number addition 8-bit Signed number addition 01001000 (+72) 10000001 (-127) 00111001 (+57) 11111010 ( -6) -------------------- -------------------- (+129) (-133) What is largest What is smallest positive number negative number represented by 8-bit? represented by 8-bit? Slide from H.H.Lee, Georgia Tech 55 Korea Univ Overflow/Underflow in Signed Numbers • So, we can detect overflow/underflow with the following logic Suppose that we add two k-bit numbers xk-1xk-2… x0 + yk-1yk-2… y0 = sk-1sk-2… s0 Overflow = xk-1yk-1sk-1 + xk-1yk-1sk-1 • There is an easier formula Let the carry out of the full adder adding two numbers be ck-1ck-2… c0 Overflow = ck-1 + ck-2 If a 0 (ck-2) is carried in, the only way that 1 (ck-1) can be carried out is if xk- 1 = 1 and yk-1= 1 • Adding two negative numbers results in a non-negative number If a 1 (ck-2) is carried in, the only way that 0 (ck-1) can be carried out is if xk- 1 = 0 and yk-1= 0 • Adding two positive numbers results in a negative number 56 Korea Univ Overflow/Underflow Detection in Signed Numbers A3 B3 A2 B2 A1 B1 A0 B0 A B A B A B A B Carry Full Cin Full Cin Full Cin Full Cin Cout Cout Cout Cout Adder Adder Adder Adder S S S S Overflow/ Underflow S3 S2 S1 S0 Cn n-bit Adder/Subtractor Overflow/ Underflow Cn-1 Slide from H.H.Lee, Georgia Tech 57 Korea Univ Recap • Unsigned numbers Overflow could occur when 2 unsigned numbers are added • An end carry of “1” indicates an overflow Underflow could occur when 2 unsigned numbers are subtracted • An end carry of “0” indicates an underflow. minuend < subtrahend • Signed numbers Overflow could occur when 2 signed positive numbers are added Underflow could occur when 2 signed negative numbers are added Overflow flag indicates both overflow and underflow 58 Korea Univ Recap • Binary numbers in 2s complement system are added and subtracted by the same basic addition and subtraction rules as used in unsigned numbers Therefore, computers need only one common hardware circuit to handle both types (signed, unsigned numbers) of arithmetic • The programmer must interpret the results of addition or subtraction differently, depending on whether it is assumed that the numbers are signed or unsigned. 59 Korea Univ ARM Flags • In general, computer has several flags (registers) to indicate state of operations such as addition and subtraction N: Negative Z: Zero C: Carry V: Overflow • We have only one adder inside a computer. CPU does comparison of signed or unsigned numbers by subtraction using adder CPU sets the flags depending on the result of operation These flags provide enough information to judge that one is bigger than or less than the other? 60 Korea Univ ARM Flags (Cont) 61 Korea Univ

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