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Final MSc Project Presentation

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Final MSc Project Presentation Powered By Docstoc
					IF Receiver for Wideband
Digitally Modulated Signals
                     Oren Avraham

  Direct Instructor: Doctor Ronen Holtzman, Microwave Division,
  Elisra Electronic Systems Ltd.
  Supervising Instructor: Professor Raphael Kastner, Department
  of Physical Electronics, School of Electrical Engineering, Tel Aviv
  University

                                                                        1
    Presentation Outline
   Objectives
   Requirements
   Block Diagrams
   Processing Features
   Research and Reading Subjects
   Results and Conclusions


                                    2
           Primary Objectives
I. Design a receiver for wideband digitally modulated signals:
     Analog processing: full circuit design
     Digital processing: algorithm principles
     Software definition (including Gain and NF evaluation for BIT)


II. Perform the required research and literary reading on various
    aspects of the analog and digital processing to assure minimal
    degradation in signal quality, among which are the following:
      Analog to Digital Converters and their proper use in the
        integrated system.
      Calculation of Sampling Clock Aperture Jitter and its effect on
        ADC SNR.

III. Realize and test a working PCB using SMT components, which
    performs the analog processing section.

                                                                         3
         System Block Diagram

             IF Section
  IF                           Analog to Digital
Input                            Converter
        (Analog Processing)




              FPGAs                                Optical
                                   Optic
                                                   Digital
                                Transceiver
        (Digital Processing)                       Output


                                                         4
             Main Requirements
   Input / Output Frequencies:
         70 MHz
         140 MHz
   4 Selectable Bandwidths per Center Frequency
   SNR degradation (IF Cascade & ADC): 0.1 dB, maximum
   Maximal Dynamic Range @ 100 KHz Resolution :
                2nd Order: 70 dB, minimum
                3rd Order: 70 dB, minimum
   Gain Control Dynamic Range:
         AGC: 30 dB
         MGC: 30 dB
   Output Power Level: Should be chosen to best utilize the
    ADC’s Dynamic Range.

                                                           5
Analog Processing: Block Diagram
                                             Pre Selector Filter bank

                                                               ByPass

                                                                 70/5

                                                                70/10

                                                                70/28
   IF
 Input                                                                                                                      Thermopad/ATT
                                                                70/40
                AT-117
                                                                140/10                                 20 dB
     HMC484      DCA
                                                                                            RF2360
                                                                                                               Power Overload
                                                                140/20                                           Detection
                                                                                                                Threshold
                                   HMC253                       140/40
          Noise
         Generator
                                                                140/56                                     IF          Comp
                                                                                                          DET

                                                                                                        AD8309

                                                                                                                 μC            Control
                                                                                                                 A/D



                                                                                            Anti Aliasing Filter
                                                    RVA2500                                                                                        IF
                               Thermopad                                                             LPF 90                                      Output
                                                         VVA

                                                                     20 dB                           140/56                              20 dB
                                            Integrator
                            AGC
                          Feedback
                                                                          IF
                                               Op                                  AD8309
                         AGC/MGC                                         DET                                                       Monitor
                                               Amp
                                                                                                                                   Output
                             μC                                D/A
                             A/D                                             μC
                                                                             A/D



                                                Control


                                                                                                                                                          6
Analog Processing: Main Features

   Automatic Gain Control
   Manual Gain Control
   Sub-Octave Filtration
   Anti-Aliasing Filtration
   Noise Injection for BIT Purposes




                                       7
    AGC/MGC (1): Circuit
                                  RVA2500
                                                          20 dB
  AGC                                                    Coupler                 AGC
                                    VVA
IF Input                                                                       IF Output
                              VVA
                             Control
                             Voltage


                                       C



                 Analog       Operational          R                         IF
                               Amplifier                     RSSI
                  AGC                       -                              Detector
                                                                          (AD8309)
                                            +
                 MGC/                           Target
                 Digital
                 AGC
           μC                                                       μC
                                                       D/A
           A/D                                                      A/D




                           PC (Control Software)



                                                                                           8
AGC/MGC (2): IF Detector
                          Log Amp RSSI Versus IF Signal Power at Cascade Output
              1.3



              1.2



              1.1



               1
RSSI [Volt]




              0.9



              0.8



              0.7



              0.6



              0.5



              0.4

                    -40     -35    -30    -25       -20     -15      -10   -5   0   5
                                                Output Power [dBm]




                                                                                        9
                            AGC/MGC (3): VVA
                                  VVA Attenuation Versus Control Voltage
                   70




                   60




                   50
Attenuation [dB]




                   40




                   30




                   20




                   10




                   0
                        0     2      4         6           8        10     12   14
                                           Control Voltage [Volt]


                                                                                     10
        Sub-Octave Filtration
   Performed by the Pre-Selector Filter Bank
  Improves the effective IP2 by at least 20 dB
  Composed of Eight Band Pass Filters:
  1. 70/5 MHz
  2. 70/10 MHz
  3. 70/28 MHz
  4. 70/40 MHz
  5. 140/10 MHz
  6. 140/20 MHz
  7. 140/40 MHz
  8. 140/56 MHz
  A Bypass channel is included for scenarios in which an
   extremely low Group Delay Variation is required.

                                                        11
         Anti-Aliasing Filtration
  Performed by two filters:
  1. LPF 90 MHz
  2. BPF 140/56 MHz
 Designed for a Sampling Frequency of 196.608
   MHz (48th multiple of an E1 rate).
 Replica Rejection for worst case scenario:
    1.    LPF 90 MHz: 70 dBc
    2.    BPF 140/56 MHz: 55 dBc




                                           12
                           Built In Test
   A Noise Generator (ENR=30 dB) is used for Noise Injection
   ADC Samples are used as observations and two noise power
    levels are computed:
        1.   N1 – Natural Thermal Noise at Cascade Input (-174 dBm/Hz)
        2.   N2 – Generator Noise at Cascade Input (-144 dBm/Hz)
   Using the following equations the IF cascade’s Gain and
    Noise Figure are evaluated:
                              N [W ]                         N 2 [W ]  N 1 [W ] 
                              N [W ]  1
    NF [dB]  ENR  10  log  2             G[dB]  10  log 
                              1
                                         
                                                              (T  T )  k  B   
                                                               h        o          
   The test scans all signal channels and produces a Pass/Fail
    report.



                                                                                   13
     Digital Processing: Block Diagram
                                                                1st FPGA
                                                           Decimation

                                    IQ              Distributed
                                 Conversion         Arithmetic
                                                       FIRs     Downsampling
IF Cascade     12-bit ADC
                                                                       ↓D          Anti-sinc Filter
  Output     @ 196.608 MHz


                  X2
              Frequency
               Multiplier           NCO


                         98.304 MHz
                       Reference Clock


                                                2nd FPGA



                                              P/S
                                                           RocketIO
                                                                               Optic TX/RX
                                                                                                      Receiver
                                                           Interface                                   Output


                                                                                                                 14
Simplified View of Sampled Spectrum
                Sampled Spectrum for a 70/40 MHz Analog Input Signal (shown for 0<f<f )
                                                                                                                                 s

               1


              0.8
  Magnitude




              0.6


              0.4


              0.2


               0
                    0   10   20   30   40   50   60   70   80   90   100   110   120   130   140   150   160   170   180   190
                                                            Frequency [MHz]
               Sampled Spectrum for a 140/56 MHz Analog Input Signal (shown for 0<f<f )
                                                                                                                                 s

               1


              0.8
  Magnitude




              0.6


              0.4


              0.2


               0
                    0   10   20   30   40   50   60   70   80   90   100   110   120   130   140   150   160   170   180   190
                                                            Frequency [MHz]



                                                                                                                                     15
     Research and Literary Reading Subjects:
    ADC-Related System Design Considerations
   The complete Receiver functions as an Integrated Analog-
    Digital System.
   A thorough understanding of the ADC’s effects on the
    integrated system’s performance is required.


   This is performed by characterizing the ADC in “RF/IF
    terms” and designing the IF cascade accordingly.
One of the main questions which arise is the following:
          What is the optimal power of the
         analog signal at the ADC’s input?
                                                            16
Input Power to ADC – Introduction (1)
   It is a wide spread notion that in order to best utilize the
    ADC’s Dynamic Range (bits), the analog signal’s power at
    the ADC’s input should be as high as possible, putting it
    very close to Full Scale Power (FSP).
   This yields very demanding Gain and Linearity
    requirements of the RF cascade preceding the ADC, and
    causes an inevitable degradation of signal integrity (higher
    gain means higher intermodulation products, harmonics,
    likelihood of compression and so forth).
   Furthermore, the risk of ADC clipping (when the analog
    signal power exceeds its FSP) runs very high.




                                                           17
    Input Power to ADC – Introduction (2)
    Our hypothesis is that it is not the analog signal’s power
     but rather the amplified Thermal Noise of the RF/IF
     cascade at the ADC’s input which determines the
     degradation in system noise performance caused by the
     ADC.
    This is based on the fact that ADC noise (Thermal,
     Quantization and Jitter Induced) can be referred to as
     white noise.
    This white noise is added to the amplified thermal noise
     (which is white is as well) at the ADC’s input.
    Since both noises are white and statistically independent,
     the result is their power summation.
    Therefore, we can calculate the ADC’s Effective Noise
     Figure.

                                                             18
Input Power to ADC: ADC Effective NF

                                 ADC FSP [dBm]
                                 Typically 1 dB below FSP [-1 dBFS]



     SNR (Integrated Over Entire Nyquist Bandwidth) [dB]




               f sampling   
     10  log 
               2            
                             
                            
                                 ADC Noise Density [dBm/Hz]
       ADC Effective NF [dB]
                                 Thermal Noise Density
                                 (kTB=-174 dBm/Hz )
                                                                      19
          Input Power to ADC – OG (1)
         In order to perform the power summation of Thermal
          Noise and ADC Noise in a more intuitive manner, we use
          the Over Gain approximation:

                     Amplified Thermal   ADC Noise: NADC
                        Noise: NRF/IF



 Natural Thermal      RF/IF                                 Combined
                                                    ADC
Noise: -174 dBm/Hz   Cascade
                                                             Noise


                       GRF/IF
                                                    NFADC
                       NFRF/IF



                                                              20
        Input Power to ADC – OG (2)
   The different Noise Power Levels are:                         OG     Δ(OG)
N ADC  174  NFADC                                              [dB]    [dB]

N RF / IF  174  GRF / IF  NFRF / IF                           <-20   ≈ |OG|
OG [dB]  N RF / IF  N ADC  GRF / IF  NFRF / IF  NFADC        -20     20.04
N Combined  N RF / IF  N ADC  N RF / IF  OG                -15     15.1
                                                                  -10     10.4
                 OG Summation
                                                                   -6         7
                          Combined Noise [dBm]                     0          3
    Δ(OG) [dB]                                                     6          1
                          Amplified Thermal Noise: NRF/IF [dBm]   10          0.4
                                                                  15          0.1
    Over Gain (OG) [dB]
                                                                  20      0.04
                                                                  >20         ≈0
                          ADC Noise: NADC [dBm]
                                                                         21
    Input Power to ADC – OG (3)
                                                       SNR
   Therefore, we can predict the ADC-        OG
                                                    Degradation
    Induced SNR Degradation based on         [dB]
                                                       [dB]
    the OG table.                            <-20     ≈ |OG|
   We note that for an OG of more than      -20       20.04
    15 dB, this degradation is negligible.   -15       15.1

   From this, we would derive the Gain      -10       10.4
    Requirement of the RF/IF Cascade          -6        7
    (for a given NF):                         0         3
                                              6         1
      GRF / IF  15  NFADC  NFRF / IF      10         0.4
                                             15         0.1
   We verified our hypothesis by            20        0.04
    simulation, as presented in the          >20        ≈0
    following slides.
                                                         22
Input Power to ADC – Simulation (1)
        High OG (20 dB), -50 dBFS Input Sine Wave:
                                  Analog Signal at ADC Input                                                                 Digitized Signal at ADC Output
                         0                                                                                     0
                                                            Analog Signal
                                                            ADC Noise Floor
    Magnitude [dBFS]




                                                                                          Magnitude [dBFS]
                        -50                                                                                   -50




                       -100                                                                                  -100




                       -150                                                                                  -150
                              0   10         20        30         40                                                0          10          20         30        40
                                           Frequency [MHz]                                                                               Frequency [MHz]

                                                                    ADC Simulation (Single Plot)
                         0
                                                                                                                                            Analog Signal at ADC Input
                                                                                                                                            Digitized Signal at ADC Output
    Magnitude [dBFS]




                        -50




                       -100




                       -150
                              0        5          10         15           20         25                                 30          35           40            45
                                                                               Frequency [MHz]
                                                                                                                                                                             23
Input Power to ADC – Simulation (2)
        Low OG (-10 dB), -1 dBFS Input Sine Wave:
                                  Analog Signal at ADC Input                                                                 Digitized Signal at ADC Output
                         0                                                                                     0
                                                            Analog Signal
                                                            ADC Noise Floor
    Magnitude [dBFS]




                                                                                          Magnitude [dBFS]
                        -50                                                                                   -50




                       -100                                                                                  -100




                       -150                                                                                  -150


                              0   10         20        30         40                                                0          10          20         30        40
                                           Frequency [MHz]                                                                               Frequency [MHz]

                                                                    ADC Simulation (Single Plot)
                         0
                                                                                                                                            Analog Signal at ADC Input
                                                                                                                                            Digitized Signal at ADC Output
    Magnitude [dBFS]




                        -50




                       -100




                       -150


                              0        5          10         15           20         25                                 30          35           40            45
                                                                               Frequency [MHz]
                                                                                                                                                                             24
Input Power to ADC – Simulation (3)
        High OG (15 dB), -90 dBFS Input Sine Wave:
                                  Analog Signal at ADC Input                                                                  Digitized Signal at ADC Output
                         0                                                                                      0
                                                             Analog Signal
                                                             ADC Noise Floor

                        -50                                                                                    -50
    Magnitude [dBFS]




                                                                                           Magnitude [dBFS]
                       -100                                                                                   -100



                       -150                                                                                   -150



                              0    10         20        30         40                                                0          10          20         30        40
                                            Frequency [MHz]                                                                               Frequency [MHz]

                                                                     ADC Simulation (Single Plot)
                         0
                                                                                                                                             Analog Signal at ADC Input
                                                                                                                                             Digitized Signal at ADC Output

                        -50
    Magnitude [dBFS]




                       -100



                       -150



                              0         5          10         15           20         25                                 30          35           40            45
                                                                                Frequency [MHz]
                                                                                                                                                                              25
Input Power to ADC – Simulation (4)
   OG Sweep (-30 dB to +30 dB), showing that our hypothesis
    coincides with the simulation results:
                                         SNR Degradation Caused by the ADC Versus Over Gain
                             30

                                                                                                  Theoretic
                                                                                                  Simulation


                             25




                             20
      SNR Degradation [dB]




                             15




                             10




                             5




                             0

                             -30   -25     -20   -15   -10   -5     0          5   10   15   20    25          30
                                                              Over Gain [dB]
                                                                                                                    26
            ADC: Effective IP3
   IP3 is the 3rd order Intercept Point, which
    corresponds to the 3rd order Intermodulation
    Products of a non-linear analog (RF) component.
   One of the ADC’s non-linearity parameters is the
    “Two-Tone Intermodulation Distortion Rejection”
    (IMDR).
   We “translate” the ADC’s IMDR to RF/IF terms
    (IP3) using the following relation:
                                      1
          IP
           3
            ADC
                 [dBm]  Pin [dBm]   IMDR [dB]
                                      2
          Pin [dBm]  Pin [dBFS ]  FSP [dBm]
                                                   27
  Effect of Sampling Clock Aperture
          Jitter on ADC SNR
   The Effective SNR of an ADC is comprised of
  several noise sources:
                                                   ADC DNL
                     RMS Aperture Jitter          (Differential         Thermal Noise
                      of Sampling Clock          Non Linearity)            in LSBs


                                                                                   2   
                                                    2  1     2 VTh , rms        
                                                             2

SNRADC    20  log    2    f signal  rms     N    N 
                                                   2
                                                                                        
                                                    3  2         2         
                                                                                       
                                                                                       
       Analog
        Signal                                   ADC Resolution
      Frequency                                  (Number of bits)
                                                                               28
Calculation of Sampling Clock RMS
         Aperture Jitter (1)
   The common approach to calculate the
    RMS Aperture Jitter of a frequency source
    (such as a sampling clock) is to integrate its
    Phase Noise as is, and simply translate the
    result (received in radians) to temporal
    terms (seconds):
                              fs       
                       2      L f df 
                             
              rms                     
                      fs   0         

                                               29
Calculation of Sampling Clock RMS
         Aperture Jitter (2)
   We apply a more modern approach which
    incorporates a sine function factor, as follows:
                                        Frequency Offset
             Oscillator Phase Noise
                                      From Center Frequency
                     (After BPF)


                         fs            f 
                                               2
                                                 
               2         L f   sin    df 
                        
      rms                            2 f 
              fs                        s 
                                                 
                         0                      
            Oscillator
             (Center)
            Frequency                                         30
    Calculation of Sampling Clock RMS
             Aperture Jitter (3)
   The sine factor attenuates the Phase Noise close to the oscillator
    center frequency, as depicted in the following figure:
                                                                  sin(/2f/f 0)2
                                   0




                                 -50
             Attenuation [dB]




                                -100




                                -150
                                     -8    -7    -6          -5          -4         -3      -2    -1    0
                                   10     10    10         10          10          10      10    10    10
                                                      Normalized Frequency Offset (f/fo)
                                                                                                            31
    Calculation of Sampling Clock RMS
             Aperture Jitter (4)
    At frequencies that are far from the center, the Phase Noise is
     attenuated by the Clock’s BPF:
                                Filter Response
            0



           -20                              Center Frequency
                                             (fs=98.304 MHz)

           -40

                                                        2fs
           -60



           -80
             50           100                     150          200
                                Frequency (MHz)                      32
Calculation of Sampling Clock RMS
         Aperture Jitter (5)
                                                Phase Noise
                       -60                                                        Before BPF
                                                                                  After BPF




                       -80
 Magnitude [dBc/Hz]




                      -100




                      -120




                      -140




                      -160




                             0    1    2    3          4            5    6    7
                         10      10   10   10        10         10      10   10
                                            Frequency Offset [Hz]
                                                                                               33
           Results (1): At 70 MHz
                                              Measurement
    Parameter      Requirement                         2nd Amp
                                 2nd Amp   Enabled
                                                       Disabled
Noise Figure,
maximum [dB]           9.5             5.2                   8.5

Expected SNR
Degradation,           0.1            <10-3                 0.085
maximum [dB]

DR2 @ 100 KHz
                       70             76.9                  85.25
BW, minimum [dB]

DR3 @ 100 KHz
                       70             72.2                   84
BW, minimum [dB]
                                                                    34
          Results (2): At 140 MHz
                                         Measurement
    Parameter      Requirement   2nd Amp          2nd Amp
                                 Enabled          Disabled
Noise Figure,
maximum [dB]           9.5         5.5                 9

Expected SNR
Degradation,           0.1        <10-3            0.095
maximum [dB]

DR2 @ 100 KHz
                       70          77              85.25
BW, minimum [dB]

DR3 @ 100 KHz
                       70          72              83.65
BW, minimum [dB]

                                                             35
                Conclusions
I. The Subject of ADC Integration with RF/IF Cascades
   was explored, reaching the following conclusions:
     The ADC-Induced SNR Degradation is determined by
      the level of thermal noise at the ADC’s input.
     Even sub-LSB signals can be detected by the ADC.
     The Over Gain approximation proved to be a good
      method to determine the required Gain of the RF/IF
      cascade and predict the SNR Degradation.

II. The Analog (IF) section of the receiver was designed,
   built and measured showing electrical performance
   surpassing the requirements.


                                                            36

				
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