# Analog to Digital Conversion

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```					Analog to Digital Conversion
A/D Conversion Techniques
Interfacing the ADC to the IBM PC
DAS (Data Acquisition Systems)
How to select and use an ADC
A low cost DAS for the IBM PC

1

   Digital Signal Processing is more popular
 Easy to implement, modify, …
 Low cost
   Data from real world are typically Analog
   Needs conversion system
 fromraw measurements to digital data
 Consists of
Filters
 Amplifier,

 Sample and Hold Circuit, Multiplexer

Chap 0                                                   2


 Number of discrete output
level : 2n
 Quantum
   Basic I/O Relationship                    LSB size
   ADC is Rationing                      Q = LSB = FS / 2n
System                        Quantization Error
   x = Analog input /          1/2 LSB

Reference               Reduced by increasing n

• Fraction: 0 ~ 1

Chap 0                                                                         3
Converter Errors
   Offset Error                      Integral Linearity Error

   Gain Error                        Differential Linearity Error

   Can be eliminated by initial      Nonlinear Error
adjustments                          Hard   to remove
Chap 0                                                                         4
Terminologies
   Converter Resolution               Conversion Time
 The smallest change                Required time (tc) before
required in the analog              the converter can provide
input of an ADC to                  valid output data
change its output code by       Converter Throughput Rate
one level                          The number of times the
   Converter Accuracy                     input signal can be
 The difference between              sampled maintaining full
the actual input voltage            accuracy
and the full-scale                 Inverse of the total time
weighted equivalent of              required for one
the binary output code              successful conversion
 Maximum sum of all                 Inverse of Conversion
converter errors including          time if No S/H(Sample
quantization error                  and Hold) circuit is used

Chap 0                                                                          5
More on Conversion Time
   Example
   Input voltage change
 Conversion Time: 100sec
during the conversion
process introduces an               Sinusoidal input
undesirable uncertainty                vi  A sin(2 ft )

   Rate of change
   Full conversion accuracy is
dvi
realized only if this                        2 fA cos(2 ft )  2 fA
dt
uncertainty is kept low
   Let FS = 2A
below the converter’s
2A
resolution                                 2 fA 
2 n tc
 Rate  of Change x tc                                 1
 resolution                             f                  12.4 Hz
dV       FS                                    2  tc
n

 ( ) max  n
dt      2 tc                      Limited to Low frequency
of 12.4 Hz
   Few Applications
Chap 0                                                                                  6
S/H increase Performance
   S/H (Sample and Hold)                  Example
 Analog   circuits that                   20 nsec aperture time
quickly samples the                            f 
1
 62.17 KHz
input signal on                                       2  ta
n

command and then                              Reasonably good for
holds it relatively                            100sec converter
constant while the
conversion
 Aperture time (ta)
   Time delay occurs in S/H
circuits between the time
the hold command is
received and the instant
the actual transition to
Chap 0               the hold mode takes                                                    7
   Typically, Differential or            Matching input signal
Single-ended input signal              and input range
of a single polarity
   Prescaling input signal
 Typical Input Range                      using OP Amp
 0 ~ 10V and 0 ~ 5V
   In a final stage of
 If Actual input signal                        preconditioning circuit
does not span Full                     By proportionally
Input range                             scaling down the
   Some of the converter              reference signal
output code never used                 If reference signal is
   Waste of converter                      adjustable
dynamic range
   Greater relative effects
of the converter errors
Chap 0               on output                                                         8
Converting bipolar to unipolar
   Input signal is scaled and an
   Using unipolar converter
when input signal is bipolar                  Add
offset
 Scaling      down the              scaled
input
 Adding an offset
   Bipolar Converter
 Ifpolarity
information in output
is desired
 Bipolar input range
   Typically, 0 ~ 5V
 Bipolar Output
 2’s Complement

 Offset Binary
Chap 0                                                                          9
 Sign Magnitude
Outputs and Analog Reference Signal
   I/O of typical ADC
   Errors in reference signal
 From

 Drift with time and
temperature
 Cause
 Gain error in Transfer

   ADC output                                     characteristics
   To realize full accuracy of
 Number of bits                          ADC
 8 and 12 bits are typical
 Precise  and stable
 10, 14, 16 bits also
available                               reference is crucial
 Typically     natural                          Typically, precision IC
voltage reference is
binary                                         used
   BCD (3½ BCD)                                • 5ppm/C ~ 100ppm/C
Chap 0                                                                                   10
• For digital panel meter,
Control Signals
   HBE / LBE
      Start                            From CPU
 From CPU                       To read Output word
 Initiate the conversion         after EOC
process                              HBE
• High Byte Enable
      BUSY / EOC
   LBE
 To CPU
• Low Byte Enable
 Conversion is in
progress
 0=Busy: In progress
 1=EOC: End of
Conversion

Chap 0                                                                 11
A/D Conversion Techniques

   Counter or Tracking ADC
   Successive Approximation ADC
 Most   Commonly Used
   Dual Slop Integrating ADC
   Voltage to Frequency ADC
   Parallel or Flash ADC
 Fast   Conversion
   Software Implementation
   Shaft Encoder

Chap 0                                      12
   Operation
   Block diagram         Reset and Start Counter
 DAC convert Digital
output of Counter to
Analog signal
and Output of DAC
   Vi < VDAC
• Continue counting
   Vi = VDAC
• Stop counting
   Waveform              Digital Output = Output of
Counter
 Conversion time is varied
   2n Clock Period for Full
Scale input

Chap 0                                                               13

   Tracking or Servo                    Can be used as S/H circuit
Type                                    By stopping desired
instant
   Using Up/Down
 Digital Output
Counter to track input
signal continuously                 Long Hold Time

   For slow varying input      Disabling UP (Down)
control, Converter generate
 Minimum (Maximum)
value reached by input
signal over a given period

Chap 0                                                                             14
   Most Commonly used in             Block Diagram
medium to high speed
Converters
   Based on approximating
the input signal with binary
code and then
successively revising this
approximation until best
approximation is achieved
   SAR(Successive
Approximation Register)
holds the current binary
value

Chap 0                                                          15
   Circuit waveform      Conversion Time
 n clock for n-bit ADC
 Fixed conversion time

   Serial Output is easily
generated
   Bit decision are made
in serial order
   Logic Flow

Chap 0                                                          16
Dual Slope Integrating ADC
     Operation                           Excellent Noise Rejection
T1
 Integrate 0 vi dt                  High frequency noise
t2          cancelled out by integration
 Reset and integrate  Vr dt
0
 Proper T1 eliminates line
 Thus T1vi ( AVG )  t2Vr
t                 noise
  v            Vr 2
i ( AVG )                       Easy to obtain good resolution
     Applications T1
   Low Speed
 DPM(Digital Panel Meter),
 If T1 = 60Hz, converter
DMM(Digital Multimeter),
throughput rate < 30
…
samples/s

Chap 0                                                                            17
Voltage to Frequency ADC
   VFC (Voltage to Frequency          Low Speed
Converter)                         Good Noise Immunity
 Convert analog input            High resolution
voltage to train of pulses
 For slow varying signal
   Counter
 With long conversion
 Generates Digital output
time
by counting pulses over a
fixed interval of time          Applicable to remote data
sensing in noisy
environments
   Digital transmission
over a long distance

Chap 0                                                                       18
Parallel or Flash ADC
   Very High speed                Homework #5-1
conversion                        어떻게 동시에 비교가
 Up to 100MHz for 8 bit          되는지를 설명하라.
resolution
 Video, Radar, Digital
Oscilloscope
   Single Step Conversion
 2n –1 comparator
 Precision Resistive
Network
 Encoder
   Resolution is limited
 Large number of
comparator in IC

Chap 0                                                        19
Software Implementation

   Implementation with      Limited Practical Use
software using               Availability of Good
microprocessor                performance with very
 Counting                    reasonable Cost
 Shifting
 Inverting
 Code Conversion
…

Chap 0                                                             20
Shaft Encoder                          Binary Encoder
 Misalignment of mechanism
   Elctromechanical ADC                       causes large error
 Convert shaft angle to digital              Ex: 011  111 (180deg)
output
   Encoding
 Optical or Magnetic Sensor
   Applications
 Machine tools, Industrial
robotics, Numerical control         Gray Encoder
 Misalignment causes 1 LSB
error

Chap 0                                                                                21
Interfacing the ADC to the IBM PC
   Interface Operations                   Using CPU Interrupt
 Most-recent-data Scheme                  CPU initiate conversion
   At end of conversion it             every time it needs new
updates an output FIFO              data
   Automatically start new            CPU can proceed to do
conversion                          other thing
   CPU read FIFO to                   ADC interrupt CPU when
acquire most recent data            conversion is complete
   CPU goes to ISR
   Start-and-wait Scheme
   CPU initiate conversion
every time it needs new
data                          See Chapter 3, For more
   CPU check EOC until            information about 8259A
conversion is finished

Chap 0                                                                              22
Interface Software
   DMA (Direct Memory
Access)
   Memory Mapped Transfers              CPU release system bus
 ADC is assigned in                 by the request of DMA
Memory Space                      DMA controller carried
   MRD, MWR signal              out data transfer by
   MOV instruction              generating the required
   More complex decoding             signals
logic
 The system bus control
   I/O Mapped Transfers                  reverts back to CPU
 ADC is in I/O Space               when data transfer is
   IOR, IOW signal              finished
   IN, OUT instruction      DMA is useful
 High Speed
   More Simple decoding
 High volume data transfer
logic
   Disk Drive interface

Chap 0                                                                         23
Interface Hardware

   Parallel Data Format              Serial Data Format
 Three state output                  Asynchronous Serial
buffer in ADC                        transmission to send
data over long distance
 To Interface ADC                     to a monitoring station
   CPU + Decoding logic               UART is commonly
• To generate Chip                 used
Select signal
• To generate Start
Signal
   Interfacing 10 or 12 bit
• To Check EOC
signal                     Transfer data in chunks
of 8 bits one after
another

Chap 0                                                                        24
DAS (Data Acquisition System)

   DAS performs the            Applications
complete function of          Simple monitoring of a
converting the raw             single analog variable
outputs from one or           Control and Monitoring
more sensors into              of hundreds of
equivalent digital             parameters in a nuclear
signals usable for             plant
further processing,
control, or displaying
applications

Chap 0                                                                25
Single Channel System
   S/H (Sample and Hold)
   Transducer                         Reduce uncertainty error
in the converted output
   Generate signal of low          when input changes are
amplitude, mixed with           fast compared to the
undesirable noise               conversion time
   Amplifier, Filters                 In Multi-channel system

 Amplify                               To hold a sample from
one channel while
 Remove noise                           multiplexer proceed to
 Linearize                              sample next one
   Simultaneous sampling
of two signal

Chap 0                                                                         26
Sample and Hold Circuits
   Care in selecting hold
capacitor Ch
 Low Value
   Reduces acquisition time
   Increase Droop
   High Value
   Minimize Droop
   Increase acquisition time
   Choose capacitor to get a
best acquisition time
while keeping the droop
per conversion below 1
LSB

Chap 0                                                               27
Commercially Available S/H

Chap 0                                28
Multi-channel System

   Analog multiplexer      Local ADCs and digital
and a ADC                multiplexer
   Low cost                Higher sampling rate

Chap 0                                                           29
How to select and use an ADC

   Range of commercially      Guidelines for using
 Use the full input range
 Use a good source of
reference signal
 Look out for fast input
signal changes
 Keep analog and digital
grounds separate
 Minimize interference

Chap 0                                                                30
Commercially available monolithic

Chap 0                                       31
Commercially available hybrid ADCs

Chap 0                                        32
A low cost DAS for the IBM PC
   Generating clock
 For starting ADC
   Multi-channel system
conversion
 Less than \$100
 For causing interrupt
 Make a pulse stream from
National                      TCLK with short pulses of
Semiconductor                 duration = ½ x BCLK/4
 Constant, repetitive              TCLK from 8253
rate                               Timer/Counter
• Wide pulse
   1000 samples/s

Chap 0                                                                   33
PC prototype
board
SCSLCT
(Start Conversion SeLeCT)
: Latched trough port 30CH
SCSLCT = H
Selection of 30AH (/E10)
start conversion
SCSLCT = L
TCLK’ start conversion

INTSLCT
(INTerrupt SeLeCT)
: Latched trough port 30CH
INTSLCT = H
EOC cause IRQ2
INTSLCT = L
No Interrupt
CPU read Status register
(Port 309H) to check EOC

Chap 0                                    34
Status Register

   For polling TCLK and
EOC signal
   Port 309H (/E9)
   Polling of EOC results
in a low level after the
data from ADC have

Chap 0                                  35
Throughput rate calculation

4.77MHz / 8
= 596KHz

Chap 0                                               36
Accuracy Calculation

   Better than 1% accuracy is ensured
   Actual accuracy with smooth input signal at room
temperature will be better than 0.5%

Chap 0                                                          37
Basic Program for Controlling ADC

Sampling rate < 200 samples/s
Because OUT and IN
instruction in Basic takes 5ms

Chap 0                                                           38
C Programming for Controlling ADC

   Sampling from ADC channel 1 at 5ms interval and sending each sampled
data point to the DAC
Chap 0                                                                              39
Homework #5-2

   Prototype board의 회로 도를 참고하여 앞의 C
program이 수행되는 과정을 해석하라
 예를들면 Outp(CNTRL,5)가 수행되면 회로도
에서 어떤 신호가 구동되는지 등….

Chap 0                                          40

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