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Reducing Routing Table Size Using Ternary-CAM

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Reducing Routing Table Size Using Ternary-CAM Powered By Docstoc
					Routing Prefix Caching in
Network Processor Design
              ICCCN’01
             Oct. 15, 2001

              Huan Liu
Department of Electrical Engineering
         Stanford University
       huanliu@stanford.edu
 http://www.stanford.edu/~huanliu
Outline
Goal: Advocate routing prefix caching
      instead of IP address caching

•   Why prefix caching?
•   Prefix cache architecture
•   How to guarantee correct lookup result
•   Experimental result
•   Summary
Motivation
• Why cache?
  – Small enough to be integrated on chip =>
    Lower on chip delay than going off chip
  – Could use fast SRAM instead of DRAM
  – Smaller capacitance loading => Fast circuit
• Why cache prefix instead of IP address?
  – Solution space is smaller:
     • # of prefixes << # of IP addresses
     • # of prefixes at a router is even smaller
     • Prefixes can be compacted
  – Data centers host thousands of web servers
 IP address caching
                                          Routing Prefix Next hop
                IP address     Next hop


Micro           192.168.10.3     3
Engine          192.168.10.5     3         192.168.10.x   3


                       IP Cache
               (Fully assoc. = CAM)
         Network Processor                   Routing Table

• Problem ??
   – Spatial locality : none
   – Temporal locality : Limited

Goal: Fully exploit temporal locality using prefix cache
   Prefix cache architecture

                                            Routing Prefix Next hop

             Prefix   Next hop


Micro         192.168.10.x 3                 192.168.10.x   3
                                 ASIC
Engine


         Prefix cache (TCAM)

         Network Processor                 Routing Table (TCAM)


                                        Prefix memory
   Alternative prefix cache arch.

                                                    RAM

             Prefix   Next hop


Micro         192.168.10.x 3     Host
Engine                           CPU


         Prefix cache (TCAM)

         Network Processor                SW Routing Table (Trie)


                                        Prefix memory
Density comparison
• IP cache                • Prefix cache
  – 32 bit tag               –   32 bit tag
                             –   32 bit mask
  – Tag comparing logic      –   Tag comparing logic
                             –   Masking logic


         One implementation (Mosaid)
• CAM                     • TCAM
  – 10T SRAM cell            – 16T SRAM cell


Rough estimate: < 2x density difference
 Key problem
 • Not all prefixes are cacheable
                      Cache               Prefix memory
                                              0*
 Lookup 000000                                         1

                              0*
                                                   0




                                                           1



 Lookup 010100
                                                   0
                 0*

                                            01010*

Wrong!! 01010* should be returned. 0* is non cacheable
  Solution #1
  • Complete prefix tree expansion (CPTE)
                      Cache                 Prefix memory
                                                       0*
Lookup 000000
                                               0                1
                                00*

                                            00*             0           1




                                                   0                1   011*
Lookup 010100
                00*                         0100*               0           1
                               01010*


                                                       01010* 01011*

         Problem: Routing table explosion
  Solution #2
  • Cache IP address instead
                                         Prefix memory
                   Cache
                                              0*
Lookup 000000
                                                       1

                            000000
                                                   0




                                                           1
Lookup 010100
                000000
                             01010*
                                                       0




                                             01010*
Problem: 1. Degrade to IP cache
         2. Extra logic to send IP when matched
            non-cachable prefix
  Solution #3
• Partial Prefix Tree Expansion (PPTE)(#1 + #2)
                      Cache            Prefix memory
                                              0*
Lookup 000000
                                          0            1
                               00*

                                       00*         0




                                                           1


Lookup 010100
                00*                                    0
                              01010*


                                              01010*
                   Explosion factor comparison
                                         original          CPTE      PPTE
                  140000

                  120000

                  100000
num of prefixes




                   80000

                   60000

                   40000

                   20000

                       0
                           maeeast   maewest        paix     aads   pacbell   oix
Simulation result
miss ratio
0.05
                                              IP only

0.04                                          NPE

                                              PPTE
0.03
                                              CPTE

0.02

0.01

   0
    512      1024          2048        4096         8192
                    # of cache entries
Summary
• Prefix caching outperform IP address
  caching because temporal locality is fully
  exploited
• We show three ways to guarantee correct
  lookup result
• Experiment result: 3x+ improvement with
  only 2x- more transistors

				
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