CE-324 FPGA based System Design

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					                     NUST Institute of Information Technology (NIIT)
                                  A center of excellence for quality education and research

CE 324/EE-440                                  FPGA-based System Design                                            Spring-2008
Prerequisite: EE-241 Digital Logic and Design                                                                      Credit Hrs: 2+1

Instructor:       Dr. Nazar Abbas Saqib                                                                Email:
Office:           Ground floor, AB-4, street 8                                                         Tel:              Ext:12
Time and Place:
Lec:Wed 01:20 -03:10 pm,Lab:Thu 11:00-12:50 pm(bicse-3B)                                                         Office Hours
Lec: fri 09:00 -10:50am, Lab: Thu 01:20-03:10 pm(bicse-3A)                                   Wednesday to Friday: 4PM to 5PM
Class Room: AB-2 room # 2                                                                    Or By Appointment via Tel / Email

Course Objective:
This course aims at providing the under-graduate electronic/communication engineering students an introduction to various ASIC
design techniques. The main focus of this course will be the study of major types of FPLDs, including their structure, complexity,
and applications in design and development of re-configurable and programmable logic. The role of FPLDs has evolved from
simply implementing the “glue-logic” to the complete realization of complex functions such as microprocessors and
microcomputers. Due to their shorter design-cycle, these devices are ideal for prototyping and their low production cost make
them competitive for small to medium volume productions. Our aim is to acquaint our students with the latest design tools and
logic design techniques with FPLDs using various entry techniques, especially the use of Hardware Description Languages such
as Verilog HDL and VHDL.

Text Books:
     •    Circuit Design with VHDL by Volnei A. Pedroni

Reference Books:
     •    VHDL: Programming by Example by Douglas L. Perry (soft copy available)

Grading Policy:

          1.   Quizzes      (5-8)                             10 %
          2.   Labs/Assignments                               10 %
          3.   Project                                        10 %
          4.   One Hour Tests (7th and 14th week)             30 %
          5.   Final Exam                                     40 %

Policy Matters:
6.  Quizzes [10%]: Several Quizzes will be conducted in class. No make-up provisions.
7.  Lab/Class-Project [20%]: There will be around 10-12 Lab sessions plus one FPGA based System Design Project. The project report plus
    presentation will be due within 6-8 weeks from the issue date. The project will mostly depend on the work done in labs.
8. Projects will be allocated after 1st OHT. Due date for the projects will be 2 weeks before the final exams.
9. Two One-Hour Tests [30%] during 7th week and 14th week.
10. Final Test [40%]
11. It is mandatory to maintain at least 75% class attendance to be allowed to sit in Final Test.

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