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I do not want to make a course about VHDL as a programming language for HW (there are a lot of books better than my words 1), because courses and specifics of languages are public and everyone can find them easily on the Net. I just want to give some suggestions recommendations by whom, starting many years ago, has had to develop an endless series of projects at different levels of complexity .
VHDL (I) http://dev.emcelettronica.com/print/51866 Your Electronics Open Source (http://dev.emcelettronica.com) Home > Blog > mauriziostefani's blog > Content VHDL (I) By mauriziostefani Created 15/07/2008 - 21:33 BLOG Electronics Firmware Other Altera/Xilinx Historically the basic group which I was working started with Altera technology and so there is a branch “love” towards this society although Xilinx (the competitor), even advance as presentation of programmable components on field, has similar technology if not better (the two companies are chasing each other with the last component). It is also true that the Altera development system is free and this pushes to their easily. For that I will use Altera design sw for this examples. Quartus Today we can not suggest MaxPlus (the old Altera development system) because it is no more supported and it is abandoned because due to the missing compatibility with the new components, it is used for old project only. We download the Quartus 7.x version, available now the v8, (www.altera.com  having a fast Internet connection), then we require a license (it’s free, and will expire 3 months later, it’s connected to the MAC address of the network board ) and we install everything. It is advisable to make a directory in Quartus area to contain all the licenses that we're going to ask. After installing everything I would test some program to make sure that we have successfully installed the program, perhaps using some small example available on the site or network (http://www.altera.com/support/examples/vhdl/vhd-add-sub.html ). Our first program Although this is not a course and I am not a teacher, it’s necessary to use a vocabulary of common terms and the simplest is to comment a small program. I would have chosen an up-down counter. In first lines there are some comments, in VHDL “—“ is used as start of comment, the comment lasts until the end of the line (the VHD source code is attached) -- General Counter then we have the libraries declaration, VHDL is a strong typed language it means that each variable assumes a “type” and than will be available only operations allowed by that type. The arithmetics libraries will be more used and they will have to be declared and enabled to be used, normally I add the lpm Altera library also for the Altera macros. LIBRARY ieee, lpm, altera_mf; USE ieee.std_logic_1164.ALL; USE lpm.lpm_components.ALL; 1 din 3 16.07.2008 11:37 VHDL (I) http://dev.emcelettronica.com/print/51866 USE altera_mf.altera_mf_components.all; USE ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Now we have to declare the entity, this is the most high level of our project and in practice is the I/O project. ENTITY counter IS PORT ( res : in std_logic; clock : in std_logic; data_in : in std_logic_vector(11 downto 0); data_out : out std_logic_vector(11 downto 0); ctr : in std_logic_vector(2 downto 0) ); END counter ; I think we can do without comment the pins names of our HW. The architecture follows entity - this part of the program is the body of the program itself and contains all the used variables, shared by the various modules that compose the architecture ARCHITECTURE Behavior OF counter IS SIGNAL ctr_i : std_logic_vector(2 downto 0); signal data_out_i : std_logic_vector(11 downto 0); As soon as we define the architecture declaration we can take in consideration the real body. There are no fixed rules, it depends on the project and previous experience. I try to divide the project in several sections, usually a section is a file, in a section there are one or more processes. Every process has two parts: combinatorial logic and sequential logic. But this is not mandatory, and everyone is free to organize the project, the best advice I can give is subdivide everything as much as possible. If the design is divided into more files or more projects we can can compile and simulate each separately and then we can easily form a final project.Given the simplicity of the project, the architecture will be based on a single process. Simulation The program is compiled and we can procede with the simulation (there are no rules; just follow the advices). Because we divided our program in many files, is possible to simulate them one at a time and this allows us an easier tweak; you have to consider that all files of each section will have the same root, i.e. if the project is called "p" it is: - a P.vhd that will be the source file; - a P.wwf that will be the stimula files (we don’t take into consideration the stimula through commands because they are more difficult to use)' - a series of files produced by the compiler named p.xxx. Let’s return to the simulation file, usually I insert in first place the reset and then the clock (if necessary more than one). Other signals follow making sure to put first the input and then the corresponding output. Help yourselves with appropriate separators between the various areas of stimula. To insert a signal is better to select the visibility on all nodes and then select which we are searching for, you will pay the penalty of having very long names but all signals are shown. In some cases it happens that the signal is not visible to the simulator, what usually happens is that for an error the compilator remove the signal because it does not produce any output; nomally is easy to understand why the signal has been removed (the signal is declared but not used, or whatever the value is that can' take the logic does not change..); in some more difficult cases all you have to do is to hook the signal to a external test pin and study why the compilator removed it. 2 din 3 16.07.2008 11:37 VHDL (I) http://dev.emcelettronica.com/print/51866 In our simulation I used: - the reset; - the clock; - the signal mode (composed of 3 bit), respectively for hold,count-up,count-down and load; - the input signal composed of 12 bit; - the output signal composed of 12 bit. In attached you’ll find the entire Quartus project to test. PROG.S.EL  Note 1: McGraw Hill - VHDL Programming by Example 4th Ed.pdf, Vhdl Reference Manual.pdf Attachment Size vhdl counter.zip  347.85 KB Trademarks Source URL: http://dev.emcelettronica.com/en-vhdl-i Links:  http://www.altera.com  http://www.altera.com/support/examples/vhdl/vhd-add-sub.html  http://dev.emcelettronica.com/progsel  http://dev.emcelettronica.com/files/vhdl counter_0.zip 3 din 3 16.07.2008 11:37
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