Analog System Design Training by pengxiang

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									About VIT University
                                                                       About VLSI design Lab                                             Course description:
           Founded in 1984 as Vellore Engineering College, the
                                                                       The VLSI Design Laboratory is equipped with                       Design, simulation and Hardware implementation of Following
institute was declared a University in recognition of its academic
                                                                                                                                         topics using TINA TI and ASLKv 2010 Starter Kit
excellence by the Ministry of Human Resources Development,                     ASIC DESIGN LAB supported by CADENCE
Government of India in 2001. The University has since grown by                      Cadence Tools with 60 User License                       •    Second-order filters
leaps and bounds – establishing excellent infrastructure spread                FPGA/SOPC Lab supported by ALTERA                             •    Self-tuned filters
                                                                               MENTOR GRAPHICS Tools with 60 User License                    •    Voltage-controlled oscillators (VCO)
over an impeccacably clean and green 250 acre campus - on way
                                                                                                                                             •    Function generators
to fulfill the vision of the founder and Chancellor Dr. G.                     ANALOG SYSTEM DESIGN LAB supported by
                                                                                                                                             •    Phase-locked loop (PLL)
Viswanathan to make it truly world class. VIT today comprises                  TEXAS INSTUMENTS                                              •    Automatic gain control (AGC)
of six constituent Schools and interdisciplinary Centers offering                                                                            •    DC-DC converter
undergraduate, graduate, post graduate and research programs           This lab is being utilized by Engineers from VLSI,                    •    Low Drop Out (LDO) regulator
upto PhD level. VIT is the first educational institution of India to   Embedded, Sensors and Mechatronics divisions for                  Design and Simulation of circuit using Cadence
get ISO 9002 certificate by the DNV of The Netherlands. It is          innovations in their Academic as well as Research projects.                Circuit Design
again the first Institute in India to get accreditation from IEE                                                                                  Simulation and Parametric Analysis
                                                                       Objective of the Training
(UK). Further it has also been accredited by NBA (AICTE) and
                                                                                                                                                  Layout Design
NAAC (UGC). In the last seven years, VIT had more than 100             The goal of this training is to provide students/ Faculty an
                                                                                                                                                  DRC, LVS
visiting professors, some of them staying 6 to 12 weeks for
                                                                       exposure to the fascinating world of analog and mixed-signal
offering accelerated courses as well as participating in                                                                                          Post Layout Simulation
                                                                       signal processing. As part of the training the participants can
Workshops and Seminars for the benefit of students of VIT and
                                                                       build analog systems using analog ICs and study their macro       Course Fee:
also the industry around.
                                                                       models, characteristics and limitations. This training focus on
                                                                                                                                         For Faculty/R&D organization
         About the School of Electronics Engineering
                                                                       system design along with basic circuit design.                             Rs. 2750/- [course fee + accommodation]
                                                                                                                                                  Rs. 2000/- [course fee only]
          The School offers B.Tech [ECE] and five M.Tech
                                                                       Who Can Attend?                                                   For Students
programs. Facilities for research leading to Ph.D. are available in
                                                                                                                                                  Rs. 2250/- [course fee + accommodation]
many emerging areas. A major emphasis in both the                                Faculty from Institution who are teaching or
                                                                                                                                                  Rs. 1500/- [course fee only]
undergraduate and post graduate program is teaching and                          proposing to teach Analog System Design
learning process. School is actively involved in R&D activities                                                                          Note: DD should be taken in favour of VIT payable at
                                                                                 Research Scholars/ Students ( UG/PG)
and has sponsored projects from various agencies like DST,                                                                                     Vellore.
ISRO (RESPOND), and BRNS etc. It has MOU’s with industries                                                                                     No. of participants restricted to 40 only.
                                                                       Last date for Registration:
and other reputed institution and R&D organization of our
country and other parts of the world.                                  On or before                  : 05-10-11

                                                                       Date of confirmation          : 07-10-11
                                  Registration Form                                                       Speakers:
Name             : ....................................................................                   Need for Analog: By
                                                                                                          Dr.K.R.K. Rao Texas Instruments, India
                                                                                                                                                                  Hands on Training
                                                                                                                                                                                          VIT
                                                                                                          ……………………
                                                                                                                                                                         UNIVERSITY
                                                                                                                                                                         On(Estd. u/s 3 of UGC Act 1956)
Department: ……………………………………………
                                                                                                          Dr. C.P. Ravikumar, Director UniTi,
                                                                                                          Texas Instruments, India
Organization :………………………………………………
                                                                                                                                                                     Vellore – 632014, Tamilnadu.India
                                                                                                          Analog Lab Set at VIT: By                                              www.vit.ac.in
                                                                                                          Mr.Sultan Ahmed, Cranes Software
Experience: …………..……………………………
                                                                                                          Analog System Design Using ASKLv2010: By                Hands on Training
Address for Correspondence:                                                                               Mr.R. Sakthivel , Asst. Prof (Sr.), VIT                        in
 ................................................................................................         Circuit Design Using Cadence: By
                                                                                                          Mr. Jagannadha Naidu K, Asst. Prof, VIT
                                                                                                                                                            Analog System Design
 ................................................................................................
                                                                                                                                                                     (10, 11, 12 October 2011)
                                                                                                            Registration form and DD send to:
                                                                                                                                                                       In Association with
  ................................................................................................          School of Electronics Engineering
                                                                                                            VIT University
                                                                                                            Vellore – 632014. TN
Email: ................................................................................................
                                                                                                            Contact No :
                                                                                                            E-mail:
Phone: ...............................................................................................

                                                                                                              Course coordinators:
Accommodation Required Yes                                    No
                                                                                                                    For further details contact
Demand Draft Details:
                                                                                                              Mr.R. Sakthivel , Assistant Professor(Sr.)                        By
Faculty                    Student / Research Scholar                                                                                                                     VLSI DIVISION
                                                                                                              Email: rsakthivel@vit.ac.in
                                                                                                              contact No: 09994627570                           School of Electronics Engineering
Amount           : …………………………………….
                                                                                                                                                                       VIT University
DD No.           : …………………………………….                                                                            Mr. Jagannadha Naidu K, Assistant Professor
                                                                                                              Email : jagannadhanaidu.k@vit.ac.in
Bank             : …………………………….……….                                                                           Contact No: 09943062343
Dated            : …………………………….……….
Signature: ……………………..……….
(Use Photocopy of the above form, if required)



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