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32nm Node USJ Metrology For Rapid Process Optimization

VIEWS: 65 PAGES: 69

									 32nm Node USJ Formation Using
   Rapid Process Optimization
            Metrology
                &
  Updates From March MRS, May
IWJT, May ECS, June IIT and June
            VLSI Sym
                 John O. Borland, J.O.B. Technologies, Aiea, HI
               Yoji Kawasaki, Renesas Technology, Itami, Japan
                     Brian Chung, KLA-Tencor, San Jose, CA
               Jeffri Halim, Frontier Semiconductor, San Jose, CA
                         Solid State Technology July 2008
 J.O.B. Technologies (Strategic                                     1
 Marketing, Sales &
 Technology)
Outline
• Introduction
    – <10nm Ultra-Shallow Junction
    – Junction “Quality” (Rs dopant activation, junction
      leakage and residual implant damage after annealing)
    – Micro-uniformity variation
•   USJ Implantation
•   USJ Annealing
•   Process Integration Issues
•   FinFET Doping
•   Summary

      J.O.B. Technology (Strategic                           2
      Marketing, Sales &
      Technology)
Design For Manufacturing: Controlling Process
Variability Key For sub-45nm Node Manufacturing!




                                                                      Delta Vt=>100mV (0.1V)!
                                                                      -Process proximity effects
                                                                      -Layout loading effects
                                                                      -Gate line edge roughness
                                                                      effects
                                                                      -Implant dopant positioning
                                                                      -Thermally induced variation
                                                                      by RTA (& msec anneal)
                                                                      Key will be
                                                                      Characterization,
                                                                      Reduction &
                                                                      Accommodation




                  T.C. Chen, IBM, IEEE Solid State Circuits Society
                  Newsletter, Vol. 20, No. 3, Sept 2006, p.5
3 Main Sources Areas Of Device Leakage
                                                           • Gate Leakage
                                                              – High-k/Metal Gate
                                                                reduce gate leakage
                                                                by >1,000x
                                                           • Source Drain
                                                             Leakage
                                                              – Engineer the location
                                                                of EOR damage to
                                                                reduce junction
                                                                leakage
                                                           • Gate Edge Leakage
                                                              – Extension/HALO
                                                                junction leakage
                                                                influenced by band to
                                                                band tunneling, HALO
                                                                dose, extension
  J.O.B. Technology (Strategic                                  abruptness and 4
  Marketing, Sales &
  Technology) et al, Philips/IMEC,
  Surdeanu                           SSDM 2004, Sept. 04        shallow EOR damage
   Advanced USJ Requirements
• Minimize Dopant Diffusion                 C.-H. Jan et al., IEDM 2005, p.65

• Maximize electrical
  activation
• “Enough” defect annealing
   – Junction leakage: Small part of
     total power, but significant for low
     power CMOS
   – High channel/halo doping greatly
     increases leakage


• Need to optimize all 3 “dimensions”
• Damage metrology:
   – Traditional - TEM, devices Slow and costly!
   – Non-Contact:
       • RsL – RS & Junction Leakage        Rapid Process
       • Thermal-wave                       Optimization

                                                           P. Timans et al., MRS 2008
                                                   25 (IBM)
          32nm Node Xj= 8-20nm so B (150eV-600eV)!




                                                               MRS March 2008
J.O.B. Technologies (Strategic   NO due to MSA micro-uniformity & unstable defects needs
                                                                                     6
Marketing, Sales &
Technology)                      post diffusion-less spike/RTA!
                                 (A/cm2)
                                   E-0


                                  E-1


                                  E-2


                                  E-3


                                  E-4


                                  E-5




J.O.B. Technologies (Strategic                                        7
Marketing, Sales &
Technology)                         IMEC, VLSI Sym 2008, paper 19.1
        E-2

        E-4


        E-6




8

    Borland, IWJT 2008
HALO Dose Effects On RsL & Diode Leakage
             SPE:Si-PAI                            SPE:Ge-PAI

           SPE:Ge-PAI     Flash:Ge-PAI RsL



                                     Flash:RsL


                                       Spike:RsL


    RsL Leakage Range

             Spike




                                                                                 9

                                                            Borland, IWJT 2008
    Outline
• Introduction
• USJ Implantation
     – Single wafer implanter design
     – Elemental species (energy, dose)
•   USJ Annealing
•   Process Integration Issues
•   FinFET Doping
•   Summary



      J.O.B. Technology (Strategic        10
      Marketing, Sales &
      Technology)
J.O.B. Technology (Strategic                                11
Marketing, Sales &
Technology)                    Kuroi & Kawasaki, USJ 2005
Greatest TW Change Is In Diagonal
Scan!




  J.O.B. Technologies (Strategic    12
  Marketing, Sales &
  Technology)
  B 500eV                           5keV Ge-PAI+B    20keV Ge-PAI+B
  TW=667                               TW=1520          TW=2900




                                     DSA 1210C
                                       TW=24           DSA 1210C
                                    Stable Defects      TW=140
JOB/IMEC                               Rs=579        Unstable defects
                                                         Rs=521

USJ
Study                              DSA+Levitor
                                    900C Spike        DSA+Levitor
                                      TW=19             900 Spike
                                   Stable Defects       TW=130
                                      Rs=627         Unstable Defects
  J.O.B. Technologies (Strategic                         Rs=616         13
  Marketing, Sales &
  Technology)
MRS March 2008
Selete Demonstration of SDE Tilt


                                                                                               ~15%




   J.O.B. Technology (Strategic                                                                       15
   Marketing, Sales & Technology)
                                    Ootsuka et al., IEEE Trans Electron Devices, April 2008, p.1042
7% Improvement Due To Gate Overlap Control




   J.O.B. Technologies (Strategic                                        16
   Marketing, Sales &
   Technology)                      Fujitsu, VLSI Sym 2008, paper 19.2
                                          Lateral Graded Single-S/D
                                                       Use Selective Poly To
                                          A1           Eliminate Facet Issues
                    B4                          B1

               A4                                     A2
                                                                    Sel. Epi                                 Sel. Epi



                    B3                           B2                                          1x dose
                                                                                           3x dose 5x dose
                                                                      SOI             7x dose
                                                                                                              8x dose
                                                                    (A&B) Terraced penta SS/D formed by 0 &
                                  A3                                45 degree twist octa (8)-mode implant

(A) Terraced triple SS/D formed by 0 degree
twist quad-mode implant




   Sel. Poly                              Sel. Poly                              Sel. Poly                      Sel. Poly
                                                                               2x dose
                                                                               4x dose

   4x dose     3x dose          1x dose
                       SOI
        J.O.B. Technologies (Strategic
                                                                                      1&3, 2&4      SOI
        Marketing, Sales &        Borland, Moroz, Wang, Maszara & Iwai,
                                                                               (B) Terraced double SS/D formed by
        Technology)
                                       Solid State Technology, June 2003       45 degree twist quad-mode implant
Gate OverLap Control: Tilt
nSDE & PAI (0o-vs-30o)




                                                      Box
                                                      Shape
             Rp=3.7nm                               Rp=3.3nm
             Xj=14.7nm                              Xj=15.3nm
             Yj=0-3.3nm                             Yj=8.3nm
             Yj/Xj=0-0.22                           Yj/Xj=0.54


                                       Sin20o=0.34x
                                       Sin30o=0.5x
    J.O.B. Technology (Strategic       Sin45o=0.71x                       18
    Marketing, Sales & Technology)
            Borland & Moroz, Semiconductor International, p.72, Apr. 03
Future: Phosphorus Replacing Arsenic?
(1keV/1E15/cm2, 0 & 30 Degree Tilt)
     0o Tilt               30o Quad Tilt             Ge-PAI & 30o Quad Tilt




      Xj=12nm                  Xj=13nm
      Yj=3-5nm                  Yj=7nm
      Yj/Xj=0.42               Yj/Xj=0.53



                                                              Xj=9nm
                   Box                                        Yj=7nm
                   Shape                V. Moroz, Synopsys
                                                             Yj/Xj=0.78
                                             (Mar. 03)
• Equipment Companies                            • Annealing Companies
  – US                                                 – US
       • Varian (VIISta-HCS & -PLAD)                      • Mattson fRTP
               – Carborane option                         • Applied laser DSA
       • Axcelis (Optima-HD)                              • UltraTech laser LSA
               – Imax (molecular dopant)
                                                       – Japan
       • AIBT (i-Pulsar)
                                                          • DNS Flash lamp (FLA)
               – EC filter so >10/1 decel ratio with
                 no energy contamination          •    Metrology For Rapid
       • SemEquip (molecular dopant)                   Process Optimization
               – B18, C7, C14, P4, etc.
                                                          • KT
       • TEL-Epion (infusion doping)                          – Thermal-Probe (TW) for
               – B2H6, GeH4                                     implant damage and after
  – Japan                                                       anneal damage recovery
                                                                (residual implant
       • SEN/Axcelis (SHX)                                      damage)
               – 40/1 decel!                              • Frontier
       • Nissin & SemEquip                                    – RsL sheet resistance and
   J.O.B. Technologies (Strategic
   Marketing, Sales &
                                                                junction leakage current
                                                                                  20

   Technology)
Outline
• Introduction
• USJ Implantation
• USJ Annealing
  – Diffusion-less dopant activation and implant damage
    recovery
  – Spike+msec, msec+spike or msec+spike+msec annealing
    sequences
• Process Integration Issues
• FinFET Doping
• Summary

    J.O.B. Technology (Strategic                    21
    Marketing, Sales &
    Technology)
DSA Laser Stitching Pattern
Effect On Device Variation!




                                   IMEC, VLS I Sym 2008, paper 19.1



  J.O.B. Technologies (Strategic                                      22
  Marketing, Sales &
  Technology)
                     300mm



                                                                3.6mm




                      50mm                                                                           3.6mm

                    JOB/IMEC DSA USJ Analysis
                                   635                                         635

                                   630                                         630

                                   625                                         625                         3.6mm
                                                                 Rs (Ohm/sq)
Rs (Ohm/sq)




                                   620                                         620

                                                                               615
                                   615
                                                                               610
                                   610
                                                                               605
                                   605
                                                                               600
                                   600
                                                                                     0   1   2   3     4      5     6   7   8   9
              -30     -20    -10         0       10   20   30
                                   Y-axis (mm)
                                                                                                      23
                                                                                                      Y-axis (mm)
                                 DSA: 5keV Ge-PAI+B




J.O.B. Technologies (Strategic
Marketing, Sales &               DSA+Spike: 5keV Ge-PAI+B   24

Technology)
fRTP RsL
& TW
Wafer                                         Line Scan Y - Axis


Map &
Line
Scan
                                              Line Scan X - Axis




                                    Rs=1.5%
                                    TW=3.6%




   J.O.B. Technologies (Strategic                                  25
   Marketing, Sales &
   Technology)
RsL & TW Map & Line Scan of Sweeping
Laser

                 Rs=2456 (1.8%)




                                                                             Peak to peak
                                                                             Rs=+/-7.5%


                                    200mm High Resolution Map - 0.5mm step

   J.O.B. Technologies (Strategic                                                  26
   Marketing, Sales &
   Technology)
                               Rs=8.5% global and 1.5% local




J.O.B. Technology (Strategic                                   27
Marketing, Sales &
Technology)
    TW=26%, Rs=8.5%              Rs=2.8%


J.O.B. Technology (Strategic               28
Marketing, Sales & Technology)
NEC & Selete IWJT 2007:Differences For
Flash & Spike Results Temperature?
  Bss (atoms/cm3)




  J.O.B. Technology (Strategic                                                                   29
  Marketing, Sales & Technology)
                                   Borland’s IWJT 2007 Joint NEC (S4-8) and Joint Selete (S4-7) papers
PAI Enhanced Activation At Lower Flash
Temperatures But EOR Damage/Leakage




                                      1175C!




  Kato et al., Selete, IWJT 2007, p.143        J. Gelpy
     J.O.B. Technology (Strategic                         30
     Marketing, Sales & Technology)
DSA Laser Requires
Deep Ge-PAI So
USJ Will Be Leaky!
                                                   IMEC agrees DSA -75C!
                                                   March 2008


  T. Noda et al., SSDM 2007, paper A-5-1, p. 712




  J.O.B. Technology (Strategic                                       31
  Marketing, Sales &
  Technology)1225C!
RsL Sheet Resistance (ohms/sq.)
 2500
                                           B500eV
                                           5keVGe+B
 2000                                      10keVGe+B
                                           20keVGe+B
                                           B18H22
 1500
                                           BF2


 1000


  500


   0    <1150C?                               >1325C?
        Low LSA        Medium LSA            High LSA
         Power           Power                Power

          Borland et al., JOB Tech/Renesas/FSM/KT, Solid State Technology July 2008
                               1.2E20/cm3




Nara et al., Selete,
ECS May 2008
          J.O.B. Technologies (Strategic    33
          Marketing, Sales &
          Technology)
               LSA power level 6


               LSA power level 5



               LSA power level 4



               LSA power level 3



               LSA powerr level 2


               LSA power level 1




Borland et al., JOB/Renesas/FSM/KT, Solid State Technology, July 2008


                                                             34
                                  RsL Junction Leakage Current (A/cm2)
                                  1.00E-03
                                                                              B500eV
                                                                              5keVGe+B
                                  1.00E-04                                    10keVGe+B
                                                                              20keVGe+B
                                                                              B18H22
                                  1.00E-05
                                                                              BF2


                                  1.00E-06


                                  1.00E-07


                                  1.00E-08
                                             SPE    Low LSA Medium High LSA
                                                     Power LSA Power Power




Borland et al., JOB Tech/Renesas/FSM/KT, Solid State Technology, July 2008
J.O.B. Technologies (Strategic                                                                         36
Marketing, Sales &
Technology)                      Borland et al., JOB Tech/Renesas/FSM/KT, Solid State Technology, July 2008
                                   <1150C----------------------------------------->1350C




     B




 5keVGe+B




20keVGe+B


  J.O.B. Technologies (Strategic                                                             37
  Marketing, Sales &
  Technology)
Thermal-wave Units
10000
                                                     B500eV
                                                     5keVGe+B
                                                     10keVGe+B
                                                     20keVGe+B
 1000
                                                     B18H22
                                                     BF2


  100
                                                                                      Stable Defects




              No anneal <1150C <1250C                           >1325C         <650C
    10
               Control            Low LSA       Medium High LSA                  SPE
                                   Power         LSA    Power
                                                Power
 J.O.B. Technologies (Strategic                                                                          38
 Marketing, Sales &
 Technology)                       Borland et al., JOB Tech/Renesas/FSM/KT, Solid State Technology, July 2008
No Ge-PAI
Residual
EOR
Damage
At <7nm

            Surdeanu et al, Philips/IMEC, SSDM 2004, Sept. 04




                   Mineji et al., Selete, SSDM 2004,
                   Sept. 04
                                                            Lower Energy
                                                            Ge-PAI &
                                                            Higher MSA
                                                            Peak Temp or
                                                            Post 950C Spike
                                                            RTA Reduces
                                                            EOR Defects
                                                            Density!
                                                                    700oC iRTP,
700oC iRTP,   700oC iRTP,              700oC iRTP,                  1100oC fRTP +
1100oC fRTP   1200oC fRTP              1300oC fRTP                  950oC Spike RTA




66nm          66nm                      66nm                        66nm


                      R. Camillo-Castillo et al., U of F, MRS Spring meeting 2008, paper E6.9
       Technology (Strategic
J.O.B. Technologies (Strategic                                                     41
Marketing, Sales & Technology)
                                 V. Moroz et al., MRS Spring meeting, paper E6.6
                                 Yeong et al., CSM, IIT-2008
J.O.B. Technologies (Strategic                                 42
Marketing, Sales &
Technology)
900C Spike 1st+FLA For Low Leakage & Complete



                                                          RsL Sheet Resistance (ohms/sq.)
            2500.00
Damage Annealing With 10keV Ge-PAI
                                                                                            2000.00
                                                                                                                                  B500eV
                                                                                            1500.00                               10keVGe-PAI+B
                                                                                                                                  B18H22
                                                                                            1000.00
Borland et al., JOB
Tech/Selete/Nanom
etrics, IWJT 2007                                                                            500.00
                   RsL Junction Leakage Current (A/cm2)




                                                                                               0.00
                                                                                                      SPE   Flash   900C+FLA 1000C+FLA     1000C
                                                                0.00100000
                                                                                                                                           Spike


                                                                0.00010000                                              B500eV
                                                                                                                        10keVGe-PAI+B
                                                                0.00001000                                              B18H22


                                                                0.00000100


                                                                0.00000010


                            0.00000001
        J.O.B. Technologies (Strategic                                                                                                                 43
        Marketing, Sales &
        Technology)
                                                                                                      SPE   Flash   900C+FLA   1000C+FLA 1000C Spike
Extension Results (Leakage)
RsL Junction Leakage Current (A/cm2)
  1.00E-02
                    B200eV
                    5keVGe+B
  1.00E-03          890eVBF2
                    5keVGe+BF2
                    4keVB18H22
  1.00E-04
                                                                                    Yamamoto et al., IWJT 2008,
                                                                                    MSA pins F in substitutional
                                                                                    site and degrades leakage!
  1.00E-05
                                                                       F effect: Noda (MRS 2008), Yamamoto
                                                                       (IWJT 2008), England (IIT 2008 P41)
  1.00E-06


  1.00E-07


  1.00E-08
                     900C spike      Spike+FLA   FLA+Spike    Flash      SPE      SPE+FLA     FLA+SPE
    J.O.B. Technologies (Strategic                                                                    44
    Marketing, Sales &                                       >1200C?
    Technology)
   Extension Results (TW)
 Thermal-wave (TW units)
200

180
                          B200eV                                    PAI-EOR Damage
160                       5keVGe+B
140                       890eVBF2
                          5keVGe+BF2
120                       4keVB18H22
100

 80                Stable Defects

 60

 40

 20

  0
       900C spike         Spike+FLA    FLA+Spike   Flash      SPE       SPE+FLA      FLA+SPE
      J.O.B. Technologies (Strategic                                                             45
      Marketing, Sales &
      Technology)                                          Borland & Kiyama, JOB/DNS, IIT-2008
TW >100 Reveals Residual Implant Damage
After Diffusion-less Flash & SPE Anneals




                                                                                       SPE   Ge+B
                                                                                  Flash      B
                                                         SPE+Flash                           Ge+BF2
                       Spike
                       Spike+Flash                            Flash+SPE
                       Flash+Spike

                                                              Good leakage with EOR damage


                                    Stable Defects Unstable Defects

   J.O.B. Technologies (Strategic                                                            46
   Marketing, Sales &
   Technology)                             Borland & Kiyama, JOB/DNS, IIT-2008
    HALO Results (Rs)
Rs Sheet Resistance (ohms/square)
 70000
65000                      20keVBF2
60000                      45keVIndium
55000                      80keVB18H22
50000
45000
40000
35000
30000
25000
20000
                                      In dopant activation limited by solid solubility
15000
                                      B dopant activation limited by dose
10000
 5000
    0
                          Spike+FLA
     J.O.B.900C spike (Strategic
            Technologies              FLA+Spike      Flash          SPE        SPE+FLA   FLA+SPE   47
     Marketing, Sales &
     Technology)
P-Halo (In, B10, BF2)
     Leakage current density




  In case of indium I/I, a leakage current was detected by RsL.
  The leakage current depend on the anneal condition.
  ⇒ High temperature annealing can reduce the leakage.
                                                                                   48
                               Mienji, Borland et al., NEC/JOB/Nissin, IWJT 2007
RsL Leakage Correlation To Diode Leakage




                           Hatem et al., VSEA, IIT-2008


   49
                                                               Leaky!               Good!




   C. Hatem, VSEA
   IIT 2008 RsL
   (PR1-vs-Ge-PAI+C)
                                                          RsL LSA-1 power <1150C
                                                          RsL SPE         <650C
                                                          RsL LSA-6 power >1350C

                20keV      10keV        5keV
                Ge-PAI     Ge-PAI       Ge-PAI

                                                    No PAI

                      Borland, Matsuda & Sakamoto, joint NEC paper, Solid State Technology, June 2002,
J.O.B. Technologies (Strategic                                                               50
Marketing, Sales &                                            Solid State Technology, July 2008
                             Borland et al., JOB Tech/Renesas/FSM/KT,
Technology)                  & Kawasaki et al., IIT 2008
J.O.B. Technologies (Strategic                                         51
Marketing, Sales &               P. Timans et al., Mattson, IIT-2008
Technology)
J.O.B. Technologies (Strategic                                         52
Marketing, Sales &               P. Timans et al., Mattson, IIT-2008
Technology)
Mattson fRTP (>1300C) Leakage Results From IMEC
& FSM For Stable Defects (diode & RsL leakage)


                                HALO+PAI




                               HALO+Anneal               IMEC:HALO

                                     PAI




                                             IMEC




                 Spike       1250 FLA   1300 FLA    800int   lower HALO   SPE
   J.O.B. Technologies (Strategic                    +FLA       FLA             53
   Marketing, Sales &
   Technology)
5keV Ge-PAI EOR+HALO >100x Leakage
                          SPE:Si-PAI                       SPE:Ge-PAI

                       SPE:Ge-PAI Flash:Ge-PAI RsL



                                            Flash:RsL


                                               Spike:RsL



                                   RsL Leakage Range
                          Spike




                  Borland, IWJT 2008
  J.O.B. Technologies (Strategic                                                              54
  Marketing, Sales &                                          Uejima et al., NEC, IWJT 2008
  Technology)
    Outline
•   Introduction
•   USJ Implantation
•   USJ Annealing
•   Process Integration Issues
    – Gate Stack Electrode Material (poly or metal) & Process
      Flow
    – eSiGe strain-Si relaxation
• FinFET Doping
• Summary



      J.O.B. Technology (Strategic                         55
      Marketing, Sales &
      Technology)
Borland’s Updated Gate & Anneal Roadmap
(MSA 1st or Spike 1st?)


                                                                                      IBM attacked
                                                                                      TSMC for still
                                                                                      using SiON/poly
                                                                                      with eSiGe at
                                                                                      32nm node at
                                                                                      VLSI Sym 2008




                                                                              IBM/AMD



                  Intel
    J.O.B. Technology (Strategic                                                           56
    Marketing, Sales &
    Technology)                    Borland, Solid State Technology, Jan. 2008, p.38
Only Intel & AMD Use eSiGe at 65nm Node!
How Many at 45nm Node? TI Still Says NO!
Also High-k? IBM LSTP
32nm Node No eSiGe




   SI news editorial 2/7/08: No eSiGe, no high-
   k/metal gate, yes immersion lithography, yes msec
   annealing
   J.O.B. Technologies (Strategic                      57
   Marketing, Sales &
   Technology)
• P+ Poly Gate Doping To Reduce Tox(inv), Every 0.1nm Counts
      –    Need B diffusion so RTA 1st then msec annealing or opposite?
      –    Poly gate pre-doping
      –    Disposable spacer (reverse S/D)
      –    Metal gate electrode
      –    Gate last (replacement gate)




Ito et al., VLSI Sym. 2003
          J.O.B. Technologies (Strategic                                  58
          Marketing, Sales & Technology)
                                         Spike 1st & msec Last Best
                                         For Poly Doping While For
                                         SDE msec 1st then Spike
                                         Best For Rs




J.O.B. Technologies (Strategic                                           59
Marketing, Sales &
Technology)
                         T. Sanuki et al., Toshiba/NEC/Sony, IEDM 2007
Poly Gate Pre-doping
With LSA Only




Narihiro et al.,
NEC, IEEE/RTP
2006, p.147

         J.O.B. Technology (Strategic   60
         Marketing, Sales &
         Technology)
But 45nm Node Process Integration Requires
Disposable Spacer And Then msec Annealing
Last!




   J.O.B. Technology (Strategic                                             61
   Marketing, Sales &
   Technology)                    Toshiba/NEC/Sony, VLSI Sym. 2007, 12A-3
LSA Strain Relaxation Limits?




 C. Cheirigh et al., MIT, ECS Trans., vol.3, no. 2, p.355, Oct. 2006


 But Fujitsu and others have reported eSiGe with LSA on
 bulk wafer (non-SOI) at VLSI Sym 2007


 Must keep msec anneal <1200C with eSiGe!


      J.O.B. Technology (Strategic                                     62
      Marketing, Sales &
      Technology)
Leakage By Ge-PAI & C co-implants into Bulk & SiGe




   63
    Outline
•   Introduction
•   USJ Implantation
•   USJ Annealing
•   Process Integration Issues
•   FinFET Doping
    – Avoid Amorphization
    – Retained Dose Limit
• Summary


      J.O.B. Technology (Strategic   64
      Marketing, Sales &
      Technology)
Intel Bulk FinFET
& Toshiba eSRAM
Bulk FinFET for                          Intel, VLSI Sym 2008 short course

sub-22nm Node




Toshiba, VLSI Sym 2006,
paper 9.2




        J.O.B. Technologies (Strategic                          65
        Marketing, Sales &
        Technology)
Beam-line Versus Plasma Retained Dose
Study For FinFET Devices (Xj=6nm & 15nm)
Intel Tri-gate H/W=1 so 45 degree tilt
• Beam-line (B, BF2, B18, As, • Plasma (BF3 & B2H6) at
   As4, P, Sb) at 1E15/cm2        1E15/cm2
    – Zero tilt
                                       Width
                                           Poly-Si
  – Top=30 degree tilt (side wall=60
    degree tilt)
  – Top=45 degree tilt (side wall=45
    degree tilt)                                               Height
  – Top=60 degree tilt (side wall=30
    degree tilt)
  – FinFET 30 degree tilt                      c-Si
  – Intel Tri-gate 45degree tilt
                                       Duffy et al.,
                                       Appl. Phys. Lett. 90,
                                       241912 (2007)
     JOB Technologies working with Nissin & IMEC on this
    J.O.B. Technology (Strategic                                        66
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    Technology)
Enhanced SDE & HALO Dopant
Activation    • pMOS
                                       – pSDE (1E15/cm2 dose limited by Bss so for
                                         FLA and LSA 6E14/cm2 is OK)
 <900C Spike/RTA                           • B: 200eV/1E15
                                           • BF2: 1keV/1E15
 <700C SPE                                 • B18: 4keV/5E13
 <1200C Flash                          – HALO (3E13/cm2 dose)
                                           •   As: 20keV/3E13
                                           •   As2: 40keV/1.5E13
                                           •   As4: 80keV/7.5E12
                                           •   Sb: 35keV/3E13
                 NEC/JOB/Nissin
                 IWJT 2007
                                   •   nMOS
                                       – nSDE (1E15/cm2 or > dose)
                                           •   As: 1keV/1E15
                                           •   As2: 2keV/5E14
                                           •   As4: 4keV/2.5E14
                                           •   P: 500eV/1E15
                                           •   P2: 1keV/5E14
                                           •   P4: 2keV/2.5E14
                                           •   Sb: 1.7keV/1E15
                                       – HALO (3E13/cm2 dose)
                                           • BF2: 20keV/3E13
                                           • In: 45keV/3E13 dose limited by Inss?
                                           • B18: 80keV/1.5E12
  J.O.B. Technology (Strategic                                                      67
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                                        JOB/DNS IIT 2008
32nm Node (Xj<10nm)
• B: 150-350eV/1E15
  – Ge-PAI+B (Xe-PAI?)
        • Ge-PAI <5keV/5E14 (optional if channeling and <1300C msec
          annealing)
• BF2: 890eV/1E15
  – Ge-PAI+BF2 (Xe-PAI?)
        • Ge-PAI <5keV/5E14 (optional if channeling and <1300C msec
          annealing)
• B18H22: 4keV/1E15
• As: <1.5keV/1E15
        • Ge-PAI <5keV/5E14 (optional <1300C msec annealing)
• P: <1keV/1E15 (is PAI needed?)
• Sb: <2keV/1E15
    J.O.B. Technologies (Strategic                                    68
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Summary: Reduce Device & Process Variation
• USJ Implantation
   – Improved single wafer implanter micro-uniformity
         • Molecular dopant species for Extension & HALO (B18H22, Sb and P4)
• USJ Annealing
   – Diffusion-less activation with improved micro-uniformity and defect
     stability (how best to integrate msec 1st or 2nd ?)
         • High temperature msec annealing in combination with diffusion-less spike/RTA (900C)
   – Metrology for rapid process optimization including micro-uniformity and
     junction “Quality” detection
         • New Thermal-wave for after anneal defect stability and residual implant damage
         • RsL for sheet resistance and junction leakage measurements with and without HALO
• Process Integration Issues
   – Gate 1st poly pre-doping or disposable spacer
   – Gate last no issue
   – Complete implant damage annealing/stable residual implant damage for
     extension and HALO implants together requires post diffusion-less spike
• FinFET Doping
   – J.O.B. Technology (Strategic issue and molecular dopants for highest quality junctions
      Retained dose                                                                  69
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