UCSD Department of Computer Science and Engineering

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The future semiconductor manufacturing technology capability summarized
in the Overall Roadmap Technology Characteristics is projected to occur
in response to economic drivers within the worldwide semiconductor
industry. The ITRS traditionally grounds its technology projections
using several generic product classes for CMOS, including SOC, ASIC,
cost-performance MPU, high-performance MPU, and DRAM.   These product
classes are further taxonomized by stages of the product life cycle,
including Introduction, Ramp, and Volume Production. Clearly, product
classes “drive” the ITRS precisely because their business, competitive,
product, retooling etc. cycles are felt throughout the semiconductor
sector. However, even as the product classes frame the ITRS, the
assumed definitions made by each TWG with regard to each given product
class (e.g., “MPU”), across the entire 15-year ITRS span, can remain
unspecified or divergent. The purpose of the present chapter is to
explicitly frame the nature of the System Drivers that drive the
semiconductor industry. We complement the ORTCs by giving concrete –
and as formal as possible – definitions and salient characteristics of
the System Driver classes that consume silicon now and in the future.
[CAN SHOW SOMETHING LIKE itrs2001-010124.ppt SLIDE 1 : ORTCs and System
Drivers are the “glue” that bring together all other technical areas of
the ITRS.]

We augment the traditional taxonomy to include five System Driver
classes:   (1) High-Volume Custom (HVC), which spans microprocessors,
DSPs, and FPGAs; (2) Application-Specific Integrated Circuit (ASIC);
(3) System-on-Chip (SOC); (4) Analog, Mixed-Signal and RF (AMSRF); and
(5) Dynamic Random Access Memory (DRAM).


Each System Driver class is characterized at length in its respective
subsection below.   Because value judgements are at work in addition to
quantitative criteria, we now give several views of the distinctions
within the System Driver taxonomy.

System Driver class is driven by particular markets for semiconductor
product (e.g., computer, wireless). [ELABORATE: Products in specific
markets are contrasted by factors such as manufacturing volume, die
size, integration heterogeneity, system complexity, time-to-market,
etc. There are accordingly very different implications for both the
manufacturing and design technologies that support product delivery…]

A second type of distinction arises from cost considerations. VLSI
system cost is equal to Manufacturing cost + Design cost (the latter,
for purposes of the ITRS, includes all Test costs). Manufacturing cost
further breaks down into non-recurring engineering (NRE) cost (masks,
tools, etc.) and silicon costs (raw wafers + processing).   In general,
system cost increase is associated with any increases in function,
#Ios, package cost, power or speed. (These factors correlate well with
each other, e.g., speed --> power --> package cost. Hence,
distinctions in previous ITRS versions such as SOC-C ("cost-driven")
versus SOC-P ("performance-driven") may be viewed as simply reflecting
a cost continuum.) With this in mind, we may measure “cost” as
“normalized transistor count”, where normalization accounts for design
difficulty (analog/RF xtor cost >> memory xtor cost), reuse (reused
logic xtor cost < new logic xtor cost, but reusable xtor design cost >
non-reusable xtor design cost), performance (logic xtor running in a
500MHz design costs more at 250nm than at 100nm), etc.
Then, if we bring in TTM and volume requirements for the design, we can
see that certain regions in the (Manufacturing Volume, Time To Market,
System Complexity) space are best served by ASIC, others by SOC, and
still others by FPGA or HVC. Yet other designs (at the extreme of
technology heterogeneity, which is a contributing factor to complexity)
will be best served by multiple-die System-in-Package (SIP)
implementation. [Footnote: describe details of “normalized transistor”,
possibly attribute to a source such as IBS or Numetrics if we work with
them, …]. Figure 2 indicates roughly how the Driver classes fall along
these axes. [ELABORATE: Should put absolute coordinates (#parts,
#months, #Mlogic-xtors). Should show a picture of how we believe the
partitioning of the space will evolve (e.g., ASIC shrinks in favor of
SOC and HVC?) ?]

A third set of distinctions, particularly useful in disambiguating ASIC
from SOC and HVC, involves the following list of questions:
   1. (something about design handoff, silicon vendor?)
   2. Can the design become an IP core on another chip?
   3. Does the design process use 3rd party or internal IP?
   4. Does the design process use tools that integrate IP?
   5. Is a hierarchical design methodology used?
   6. Is the design multi-purpose and reconfigurable?
   7. Does the design contain instances from two or more Driver

[These examples are very specific, and aim to distinguish an SOC from
an ASIC. E.g., “If you answered Yes to more than 7 out of 10, then
your product is an SOC…” However, we could try to extend this set of
questions (perhaps to 10-15 questions) and show typical profiles of Y/N
for each of the Driver classes. The result could be shown as a table
of {Drivers} X {Questions}, with “x” marks in every (Driver,Question)
cell that has a “yes” answer.]

                 Vol      DRAM
                                 HVC   SoC        S
                         ASIC                     I
                                             Complexity in
           TTM                               normalized
Finally, a fourth set of distinctions may be developed by examining the
market or business objectives that shape given Driver classes, as well
as the consequences or phenomena that are demanded by other Driver
classes. For example, HVC and DRAM demand rapid process scaling;
alternatively, cost objectives are behind the very existence of SOC and
ASIC. [CAN SHOW SOMETHING LIKE itrs2001-010124.ppt SLIDE 4 (see
comments in the slide), only “unrolled” into a depiction of a directed
bipartite graph. Such a directed bipartite graph also may be depicted
as a {Factors} X {Classes} table, with 1’s indicating “drives” or “is
driven by” (adjacency matrix of the directed bipartite graph).   Note
that “Factors” break down into “objectives” (which drive particular
system driver classes) and “consequences/phenomena” (which are demanded
by particular system driver classes).]
       Market Drivers                       ASIC                    Analog                    Custom                       SoC                    Memory
Portable & Wireless                                                                                                                          Increased demand for
                                                                                                                  Increasing need for full
1. Size/weight: peak in 2002         Majority of designs.     Voice processing, RF      Specialized cores that                                memory as multiple
                                                                                                                   SoC integration.
2. Battery life: peak in 2002        Low Power design          A/D sampling move        optimize function/W.                                 functions (phone,
                                                                                                                  Increased demand for
3. Function: 2X increase every 2      paramount.               on-chip.                                                                       internet access,
                                                                                                                   digital domain
      years                                                                                                                                   address book, PDA,
                                                                                                                   receivers (DSP),
4. Time-to-Market: ASAP                                                                                                                       camera, etc.) are
                                                                                                                   -processor, and
5. Time-in-Market: decreasing                                                                                                                 integrated including
                                                                                                                   standard IO cores.
1. Bandwidth: 2X every 9 months
2. Function: 20%/year increase
3. Deployment/Operational Cost:
4. Reliability: asymptotic to
      99.999% target
5. Time-in-Market: long
Internet Switching                   Increased use of large
1. Bandwidth: 4X every 3-4 years.     FPGA to
2. Reliability                        accommodate current
3. Time-to-Market: ASAP               custom functions.
Mass Storage                         Shift toward large       Increased requirement     Increased demand for      Integration of
1. Density: 60% increase per year     FPGA and full            for higher precision      high-speed hardware       packaged function in
2. Speed: 2X by 2005                  supported vendor tool    position measurement      for functions such as:    areas such as storage
3. Form factor: Shift towards 2.5"    sets, away from ASIC     and "inertia              - "look-ahead" for        “leveling”, access
                                      costs and design         knowledgeable"               database search        control, back-
                                      flows.                   actuator power            - P instruction pre-     up/archive, real-time
                                                               controllers integrated       fetch                  virus filtering, access
                                                               on-chip.                  - data compaction,        pattern modeling (anti
                                                                                         - signal to noise         ciber-war predictors /
                                                                                            monitoring             countermeasures) will
                                                                                         - failure prediction      grow.
                                                                                         - etc.
Consumer                             Becomes the              Increased integration     Decreased interest in     Increased demand for       Increased use of
1. Cost: asymptotic down              "integration glue"       of analog resulting       long design               cores" such as:            embedded memory
2. Time to Market: <12 mo.            connecting available     from voice, visual,       cycles/high cost non-     - 3d graphics              (hardware-software
3. Function: high novelty             "intelligent" cores.     tactile and physical      prepackaged               - CPU/MMU/DSP              co-design).
4. Form factor                                                 measurement               functions or design       - Voice synthesis         Major increase in
5. Durability / safety                                         ("communicating           flows.                    - Voice recognition        demand of flash
6. Conservation / Ecology                                      sensors” for                                        - RTOS kernels             memory.
                                                               proximity, motion,                                  - Parallel processing
                                                               positioning).                                       - etc.
Computer                             Increased demand for     Simple A/D & D/A          High-speed (10X every     Development of             Demand for system
1. Speed: 10X increase every 10       digital capacity.        incorporation.             10 years) custom         custom hardware at        memory will grow by
      years                                                   Video interfaces for        processors developed     low-end continuing to     2X every 2 years.
2. System memory: 2X every 2                                   automated camera           by fewer companies.      move to purchase and      High-speed (work
      years                                                    monitoring, video        Increase in industry       integration of custom     stations and servers)
3. Power: Flat to decreasing                                   conferencing.              partnerships on          off-the-shelf P and      and low-power
4. Form factor: Shrinking size                                Integrated high-speed       common designs to        I/O cores.                (portables) memory
                                                               A/D, D/A for               reduce development                                 requirements will be
                                                               automated                  costs requiring                                    paramount.
                                                               instrumentation            ability to share data
                                                               monitoring and             and reuse across
                                                               logging, and range-        different design
                                                               speed-position             systems.
Automotive                           Becomes the              Increased integration                               Increasing use of          Increased design of
1. Functionality                      "integration glue"       of analog resulting                                  standard hardware         features using
2. Ruggedness (external               connecting available     from voice, visual and                               platforms with real       embedded software
      environment)                    "intelligent" cores.     physical measurement                                 time OS kernel and        (hardware-software
3. Reliability / safety                                        ("communicating                                      embedded software.        co-design).
4. Cost                                                        sensors” for
5. Increased amounts of embedded                               proximity, motion,
      SW                                                       positioning).





SUBSECTION 1: What is an SOC?

    “System-on-chip” is a term that addresses the productivity gap
arising from the high levels of integration that are possible as
technology scales and the shortfall in designer productivity in terms
of a normalized transistor count per designer per month. Current
perceptions are that this perceived gap will widen drammatically over
time unless there is a significant change in the methodologies, tools
and framework for design. The paradigm shift in the design process is
characterized as “SOC design” and involves re-usability to a high
degree wherever possible. The basic concept is to build a system from
reusable IP, from either 3rd parties or internally generated blocks, to
the extent possible, and combine them with proprietary IP to create the
intended system. A higher level of reusability can achieved for a given
application using a platform-based design approach where several
derivative designs can be rapidly implemented from a single platform
that has a fixed portion and variable portion for proprietary or
differentiated blocks.

Of course, SOCs are also distinguished by other factors. As a system-
on-chip, they are often mixed-technology designs, including such
diverse combinations as embedded DRAM, high-performance or low-power
logic, analog, RF, and even more esoteric technologies like Micro-
Electro Mechanical Systems (MEMS) and optical input/output. However,
design productivity is a key requirement. Design reuse will grow as a
major tool in achieving the target productivity requirements. This is
particularly true for the SoC category, where time-to-market (TTM) for
a particular capability is a key requirement of the designs.

The building blocks combined to form the SOC may be a controller core,
embedded SRAM memory, and some dedicated logic. In some cases specific
components/technological features may be added such as embedded Flash,
embedded DRAM, MEMS ,chemical sensors, or ferroelectric RAM (FRAM). The
particular expectations for such mixed technologies are included below
in Figure 1.

The process complexity will be a major factor in the cost of the SOC
applications. The more combinations of technologies that are assembled
on a single chip, the more complex the processing will be. The total
cost of processing will be hard to predict for these new materials and
combinations of processing steps but an attempt at estimating this is
  shown in Table 1. The number of such additional technological features
  on a specific SoC is likely to be limited to one or two for cost

        Figure 1 Technologies Integrated on SoC in the Standard CMOS Process

        CMOS RF
Chemical sensors
                      98          00          02        04          06         08        10          12

  Table 1      Additional Process Complexity for SoC Technologies

    Cost of adding
    technology in units                                   CMOS                                Chem.   Electro-
    of mask levels      Logic     SRAM Flash         DRAM RF   FPGA            MEMS FRAM      Sensors Optical
    Logic                 0
    Sram                   1-2          0
    Flash                   4          3-4     0
    DRAM                   4-5         3-4    7-9      0
    CMOS RF                3-5         5-9    6-9     6-10    0
    FPGA                    2          2-4    4-6     3-7    5-7         0
    MEMS                   2-10        3-12   6-14    6-15   5-15    4-12        0
    FRAM                   4-5         3-4    7-9     2-3    7-10        6-7    9-15    0
    Chem. Sensors          2-6         3-7    6-10    6-11   5-11        4-8    4-16   6-11      0
    Electro-Optical        5-8         6-9    9-12    9-13   8-12    7-10       7-18   9-13     7-14      0

  Table 1 shows an estimate of the increasing complexity of the new
  combinations of technologies in the units of extra lithography mask
  levels necessary to add this technology to the standard CMOS logic
  technology. The data in this table illustrates that the embedded
  additions of technologies add significant processing complexity and are
  compounded as the technologies are added together. The addition of
  more than two embedded technologies would increase the complexity

  SUBSECTION 2:        Discussion of SOC nature, market, past, future… with
[This is probably subsumed by the Introduction section that covers all
Driver classes.   I.e., Subsection 2 may not be needed. Refer back to
Bill Joyner for comment…]

SUBSECTION 3: What market forces drive SOC?

A number of market forces are driving the evolution of SOC design. The
most critical one is the need to improve designer productivity through
re-usable design methodologies. This driver is creating a market
opportunity for reusable IP, new design methodologies, verification,
test, etc. Secondary drivers are TTM and cost, as described in an
earlier section. While these are typical drivers in all categories of
design, both play a role in the way the designer productivity is
improved. The two design drivers in SOC are high-performance and low-
power. That is, a typical SoC will fall into one of these two
categories. In the category of high-performance, examples would be
network processors or routers, DSP and high-end gaming applications. In
the low-power arena, portable and wireless applications such as PDAs or
digital camera chips would typify SoC application areas. In either
case, there is a need for high levels of integration to build these
systems on a single chip. Finally, the need to build heterogeneous
systems is driving SoC beyond CMOS to merge with MEMS , optoelectronic
and chemical sensor technologies.

A summary of the drivers for SOC design are as follows: [NOTE: this
follows the “fourth set of distinctions” noted in the Introduction,
derived from the directed bipartite graph sketched in itrs2001-
010124.ppt SLIDE 4.]

  -   portable, wireless applications: low-power
  -   networking applications: integration
  -   TTM
  -   Cost
  -   need to improve designer productivity: reusable
  -   Heterogeneous integration
  -   High-integration

SUBSECTION 4: For what factors is SOC a principal driver?

There are a number of efforts that are driven by the development of SOC
design methodologies. It is clear that the main goal of SOC is to
achieve high integration through high productivity. This is
accomplished through design methods that promote reusability and
therefore, the tools, reusable blocks, and infrastructure for reuse
will be accelerated. SOC is a strong driver for industry standards on
IP description, testing, interfaces, verification, etc. SOC design
promotes the use of built-in self test, and perhaps built-in self
repair strategies to improve the testing of large complex designs. It
also enhances the ability of designers to optimize the chip and package
solution for the overall system. Finally, the generalization of SOC
implies the integration of a number heterogeneous technologies and
therefore SOC will be a driver for the convergence of these
technologies in the same system. A summary of the factors driven by
SOC follows:   [NOTE: this also follows the “fourth set of
distinctions” noted in the Introduction, derived from the directed
bipartite graph sketched in itrs2001-010124.ppt SLIDE 4.]

  -   High-integration/Chip size
  -   Reusability
  -   Standards
  -   Co-optimization of chip/package deployment
  -   Heterogeneous integration

SUBSECTION 5: What are some key figures of merit for SOC?
(This is the important one!   Here is where each Driver class will have
its own metrics, its own plots / trajectories, tables, etc.)

  -   Productivity Metric (norm. trans/per designer/per month) This FoM
      addresses the expected/desired improvements in productivity of
      designers. It is dependent on the availability of reusable IP,
      SoC tools, automatic BIST insertion, etc. These types of events
      will affect the trend of this FoM. It can also be measured on a
      chip by chip basis to assess overall productivity in a design.
  -   Reuse Metric – (% of chip designed with reusable blocks)
      (Japanese STRJ group has a figure showing that constant design
      team size implies zero-cost transistors (i.e., memory) must
      eventually dominate the available chip area. Note that reuse
      productivity (as distinguished from “new logic productivity”) is
      implicitly taken care of by the concept of “normalized
      transistor”. It may be more convenient to separately call out
      “reused” vs. “programmable” vs. “new logic” vs. “analog/RF” types
      of transistor.
  -   Norm Cost (NRE+marginal) relative to a baseline cost
  -   Power efficiency (MIPS/mW)
  -   Testability or diagnosability – This metric will have to be
      developed in conjunction with the Test working group