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Backside Circuit Edit on Full-Thickness Silicon Devices

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					                     Backside Circuit Edit on Full-Thickness Silicon Devices
                                                          Chad Rue
                                                 FEI Company, Hillsboro, OR, USA

                                           Steven Herschbein and Carmelo Scrudato
                                            IBM Corporation, Hopewell Jct., NY, USA



                        Introduction                                μm are occasionally observed. [8,9] The die distortion leads to
                                                                    strain, which can cause cracks and fractures in the silicon
Circuit Edit (CE) is a widely-established technique employed        during mechanical grinding and polishing.
by semiconductor manufacturers. CE reduces Integrated
Circuit (IC) development costs by reducing the number of            All of these limitations lead to the following questions: Can
mask sets that are required during the design-debug phase,          backside CE be performed on full-thickness silicon devices?
and speeds overall time-to-market.                                  Is it possible to skip the global thinning step? What are the
                                                                    advantages and disadvantages of this approach?
Most CE activities are performed with Focused Ion Beam
(FIB) tools, which have evolved considerably over the years         In this paper we will explore these questions. Sample trenches
to meet the needs of the CE market. One of the most                 will be shown, and trenching optimization experiments are
significant technique developments that has pushed the              described. We will address the issues of navigation, including
evolution of FIB hardware is the advent of backside CE              IR imaging through full-thickness silicon, and how it depends
techniques, [1,2,3] in which the FIB operator accesses the          on the sample doping levels. Finally, we will present data on a
critical circuitry through the backside (substrate side) of the     new navigational technique that can be employed to improve
IC device. This approach is the overwhelming preference for         targeting accuracy.
processor manufacturers in particular, due to the unique
constraints of these devices. For example, FlipChip and BGA                         Results and Discussion
style packages naturally lend themselves to a backside
approach. Additionally, these devices tend to have extremely        Use Cases. There are several situations in which the FIB
dense circuitry and an abundance of “dummy” metallization           operator may wish to skip the global thinning step. The most
structures that impede frontside access.                            common example is when the silicon substrate is distorted, as
                                                                    depicted in Figure 1.
Backside CE usually requires a considerable amount of
preparation prior to the actual FIB edit.[4,5] If the device is
covered with a heat-spreader, it must be removed to access the
silicon. The substrate silicon is then thinned to somewhere
between 30 and 150 μm of remaining silicon, depending on
the nature of the FIB that will be used for the edit. This limits
the time that must be spent “trenching” (milling with the ion
beam) through the substrate silicon. Next, the silicon surface
is carefully polished to a mirror-smooth finish. This ensures
IR transparency, which is important for navigational purposes
during the FIB edit. Finally, some labs perform a final
chemical etching step using laser-based tools, to locally thin
the silicon even further (to around 10 μm of remaining
silicon) over the sites of interest. [6,7]

The sample preparation required for a typical backside edit is
a significant barrier for some labs, as it requires specific
hardware and considerable operator expertise. Additionally,
the process is time-consuming and occasionally fatal to IC
devices. Finally, even with the proper hardware and operator
know-how, there are instances in which it is not possible to
                                                                    Figure 1: This graph illustrates height differences (in
mechanically thin the silicon in the typical fashion. For
                                                                    micrometers) in the silicon of a BGA-style device. The Z-axis
example, some modern IC devices are packaged on flexible
                                                                    has been greatly exaggerated.
plastic substrates. These package types tend to warp the
silicon die, and corner-to-center height differences over 100
The “pin-cushioning” distortion shown in Figure 1 is common
in modern flip-chip plastic ball grid array (FC-PBGA)
packages. These distortions arise due to differences in the
coefficients of thermal expansion of the various materials in
the package. Corner-to-center height variations in excess of
100 μm have been observed, resulting in significant stress on
the silicon. When the operator attempts to globally thin
devices under stress, they may fracture. In such cases, a full-
thickness approach may be the only option.

In other cases, the act of globally thinning the silicon may
alter key characteristics of the sample. In a recent example, an
analysis was being performed on a device with suspected
delamination problems. Mechanical polishing would almost
certainly have perturbed the delamination phenomenon, and
the analysis would have been inconclusive. Instead, the full-
thickness device was loaded into the FIB, and trenching was        Figure 2b: The corresponding optical image of the sample.
performed to remove the silicon over one of the suspected          Delamination artifacts are clearly visible after the substrate
delamination sites. Once the substrate had been removed, the       silicon was removed with the FIB.
delamination phenomenon could be examined with an optical
microscope.                                                        Finally, globally-thinned devices are thermally and
                                                                   mechanically fragile compared to their full-thickness
                                                                   counterparts. They may be too weak to tolerate mechanical
                                                                   socketing for electrical testing, and they may not be able to
                                                                   dissipate heat as effectively. Both scenarios may destroy the
                                                                   device during electrical testing.




                                                                   Figure 3: Electrical testing on devices with thinned silicon
Figure 2a: Top-down FIB view of a full-thickness device in         can result in heat build-up and catastrophic failure.
which all of the substrate silicon has been removed by FIB
trenching.                                                         The mechanical and thermal limitations of devices with
                                                                   thinned silicon can often be overcome by rebuilding the
                                                                   package prior to electrical testing. [10] When this is not
                                                                   possible, it may be a preferable to leave the silicon thick.

                                                                   Finally, a significant amount of hardware and operator
                                                                   expertise is needed to successfully thin devices. If a robust
                                                                   methodology can be developed for full-thickness backside CE,
                                                                   then some FIB labs may want to reconsider their work flow,
                                                                   and weigh the pros and cons of the full-thickness approach.
IR imaging. When a sample is initially loaded into the FIB          Note that despite a poor surface quality (Figure 4a), the IR
tool, IR microscopy is used to image the circuitry through the      image is quite clear, even though the silicon is very thick in
silicon, in order to locate the region of interest. Typically,      this case (about 550 μm).
thinner silicon results in a better IR image, which is one of the
primary reasons the die is thinned prior to backside CE.            Another example is shown in Figure 5. The initial image
However, it is not always necessary to have thin silicon to         obtained through full-thickness silicon (about 770 μm) is
obtain a suitable IR image. The images depicted in Figure 4         adequate for coarse navigation. However, the image quality is
were obtained with a high-performance IR microscope (VDS            considerably better when the silicon is thinner.
Vosskühler, GmbH) and a standard broadband microscope
illumination source (Olympus Corporation, Japan).




                                                                    Figure 5a: IR image of circuitry through about 770 μm of
                                                                    silicon.


Figure 4a: IR image of the surface of a 550 μm thick silicon
sample. Note the visible scratches in this image, which has a
horizontal field width of 96 μm.




                                                                    Figure 5b: IR image of circuitry through about 10 μm of
                                                                    silicon.

                                                                    In addition, the quality of the IR image depends on the amount
                                                                    of doping in the silicon. Very heavily doped-substrates absorb
                                                                    more IR light, and result in poorer images. Users may wish to
                                                                    experiment with their devices to see what thickness of
                                                                    remaining silicon yields acceptable optical imaging.
Figure 4b: Corresponding IR image of the circuitry, viewed
through 550 μm of silicon.
                                                                Coarse Navigation. The initial navigational step in a full-
                                                                thickness backside CE is similar to that typically performed in
                                                                conventional backside CE: the IR microscope is used to view
                                                                through the silicon and locate features in the corners of the
                                                                die. For convenience, FIB marks can be placed on the top-
                                                                surface of the silicon (directly over the location of the lock
                                                                points), so that subsequent relocking can be done quickly in
                                                                the FIB, as shown in Figure 6.

                                                                After performing the coarse 3-point lock, the stage is driven to
                                                                the approximate location of the target site. Figure 7 shows an
                                                                IR image of a target area, viewed through 550 μm of silicon,
Figure 6: IR view of a corner fiducial (left), and the
                                                                and the corresponding image with CAD overlay.
corresponding top-surface FIB mark (right).
                                                                Note again, that a great deal of circuitry structure is visible
                                                                through the thick silicon. However, some devices with higher
                                                                doping levels pose a greater challenge. We recently examined
                                                                a processor device that was thinned to 100 μm and carefully
                                                                polished. Because the silicon was heavily doped, the resulting
                                                                visibility was poorer than the images shown in Figures 4-7. In
                                                                extreme cases, the optical image may not be good enough for
                                                                coarse navigation.

                                                                Trenching. Once the approximate location of the target is
                                                                located, the silicon must be removed. Trenching through
                                                                several hundred microns of silicon requires specialized gas-
                                                                delivery hardware. In these experiments, we utilized a
                                                                standard FEI Gas-Injection System (GIS) canister containing
                                                                XeF2. The addition of XeF2 increases the rate of silicon
                                                                removal,[11] because of the following chemical reaction:

                                                                    (1) 2XeF2(g) + Si(s) → SiF4(g) + Xe(g)

                                                                The standard delivery needle was replaced with a co-axial
Figure 7a: IR view of an edit target location, viewed through   style needle which optimizes gas delivery by providing better
550 μm of silicon.                                              gas flow symmetry and higher gas flux to the sample surface.




                                                                Figure 8: Cross-sectional view of the coaxial gas nozzle used
                                                                in these studies. Note that the central vertical bore is wider at
                                                                the bottom of the nozzle than at the top. This design
                                                                concentrates the gas flux at the sample surface.
Figure 7b: The same view, but with CAD overlay.
In addition to specialized gas-injection hardware, other factors                              molecules without gas depletion. In this way, the chemistry is
can also affect trenching results on full-thickness devices. For                              allowed to do most of the work.
example, milling rates are maximized by the following
conditions:
                                                                                                                               2.0E+05
                                    A.      Higher beam currents
                                    B.      Higher XeF2 gas pressures                                                          1.9E+05




                                                                                                 Si Removal Rate (um^3 /min)
                                    C.      Lower nozzle heights
                                                                                                                               1.8E+05
                                    D.      Shorter loop times
                                                                                                                               1.7E+05
Factors A and B are obvious to experienced operators, but
factors C and D may not be so obvious. Factor C, lowering the                                                                  1.6E+05
nozzle height, results in higher local pressures at the sample
surface for a given gas flow rate. Nozzle height can have a                                                                    1.5E+05
marked impact on the milling speed, as depicted in Figure 9
below.                                                                                                                         1.4E+05

                                                                                                                               1.3E+05
                                  2.0E+05
                                                                                                                                         0   100     200    300    400      500   600
                                                                                                                                                   Pattern Loop Time (ms)
   Si Removal Rate (um^3 / min)




                                  1.5E+05                                                     Figure 10: XeF2-assisted silicon removal rates for a 100x100
                                                                                              μm pattern, performed with a beam current of 21 nA, as a
                                                                                              function of pattern loop time.

                                  1.0E+05
                                                                                              By carefully controlling the above-mentioned factors, it is
                                                                                              possible to trench through thick silicon substrates in a
                                                                                              reasonable amount of time. The trench illustrated in Figure 11
                                                                                              was milled through 550 μm of silicon.

                                  5.0E+04
                                            0             50              100           150
                                                   Height of Nozzle Above Sample (um)



Figure 9: XeF2-assisted silicon removal rates for a 100x100
μm pattern, performed with a beam current of 21 nA, as a
function of nozzle height.

Pattern loop time is defined as the period of time before the
beam repeats a scan of a milling pattern. Loop time increases
as dwell time increases and as pixel spacing decreases. Longer
loop times result in more ion dose per raster. During gas-
assisted processes, longer loop times are more likely to have
gas depletion problems. That is, the adsorbed gas precursor
molecules may be consumed before the end of an individual
pixel event. This reduces the chemical component and
increases the sputtering component of the FIB mill, resulting
in a loss of efficiency and/or selectivity. This phenomenon is
illustrated in Figure 10.

Note that as the loop time increases, the silicon removal rate                                Figure 11: FIB view of a circular trench milled through 550
decreases. This indicates that longer loop times are suffering                                μm of silicon. The diameter of the milling pattern was 200 μm.
from gas-depletion, and that too much time is spent                                           Endpoint was achieved after 44 minutes of milling time. The
performing straight sputtering under those conditions. By                                     sample was imaged with a slight stage tile (21˚) to give a
contrast, shorter loop times spread the beam out over more                                    sense of the aspect ratio.
area per unit time, allowing dissociation of the XeF2
This trench took approximately 44 minutes of milling time,      trenching process by viewing the outline of the active
and was performed with the following conditions: Beam           diffusion wells in the live milling image. This technique is
current = 21 nA, ion energy = 30 keV, dwell time = 200 ns,      often used in backside CE, but it is considerably more difficult
pixel overlap = -25%, refresh time = 0, XeF2 pressure (as       to detect on full-thickness trenches (where the aspect ratio is
measured by the primary chamber gauge) = 1.2e-5 Torr.           higher and specialized gas nozzles must be used).
                                                                Nevertheless, this result is encouraging and suggests that it is
Two more examples of trenches milled through thick silicon      possible to use this common endpointing technique on some
devices are shown in Figures 12 and 13.                         full-thickness backside edits.




Figure 12: Top-down FIB view of a trench milled through
about 770 μm of silicon. This mill took approximately 70        Figure 14a: Top-down view of the trench shown in Figure 13.
minutes of milling time with 21 nA of beam current.             Note the visible details of the active wells in the bottom half of
                                                                the trench.




                                                                Figure 14b: The diffusion wells of the active circuitry have
                                                                been exposed, which provides a visible endpoint signal (this
                                                                image has been contrast-enhanced)

Figure 13: FIB view of a square trench milled through 550
μm of silicon. The sample was imaged with a slight stage tile
(25˚) to give a sense of the aspect ratio.

The trench shown in Figure 13 is significant, because we were
able to use visual endpoint detection techniques during the
Local Navigation. Because of the long trenching times               As few as one local alignment point will work, but three
required for a full-thickness backside CE, it is not practical to   points are preferred. After locating the local alignment points
physically expose the corner fiducials with individual              with the IR microscope, the features are physically exposed
trenches. However, as described above, IR microscopy can be         using the ion beam. The CAD overlay is then applied to a FIB
used to coarsely locate the primary trench over the edit site.      image that simultaneously encompasses both the target site
                                                                    and the local alignment point (or points). For the example
Prior to attempting a critical edit, it is necessary to perform a   shown in Figure 16, a horizontal field width of 179 μm was
more precise local stage lock. We present here a new                chosen.
technique that allows high navigational accuracy using
features found locally in the bottom of the edit trench.

First, the IR image is used to locate a number of features
within the trench that will serve as local alignment points.




                                                                    Figure 16: FIB image of a coarse trench with CAD overlay.
                                                                    Three small mills have been performed to physically expose
                                                                    features that will be used for a local alignment.

                                                                    At this point in a typical backside edit, a simple one-point
Figure 15a: FIB view of a coarse trench, with CAD overlay.          correction is used to shift the CAD information to obtain a
The circles mark areas that will be used for local alignment.       better overlay to the FIB image. However, a careful analysis
                                                                    of different parts of the FIB field-of-view may reveal that a
                                                                    simple one-point correction is inadequate. In Figure 17, digital
                                                                    magnification is used to illustrate the discrepancies between
                                                                    the FIB image and the CAD overlay.

                                                                    Note that each of the three regions has a slightly different
                                                                    offset error. These different errors can arise from many
                                                                    sources: operator error in the original stage lock, imprecise
                                                                    calibration of the FIB image (magnification and/or rotation),
                                                                    local die distortions, or non-linearities in the ion column
                                                                    deflection system, to name a few. Whatever the source of the
                                                                    errors, it is usually impossible to achieve perfect
                                                                    correspondence between a CAD overlay and every point
                                                                    within a large field-of-view FIB image. Ultimately, these
                                                                    errors can limit the accuracy of the final navigational step.




Figure 15b: IR image of one of the local alignment features.
                                                                  Using digital magnification, the user can zoom-in on the FIB
                                                                  image and CAD overlay and specify a local offset for various
                                                                  regions within the image. Figure 18 illustrates how the local
                                                                  offsets could be defined for three regions in our example.

                                                                  After the 3 local offsets are defined, the CAD overlay is
                                                                  stretched, rotated and/or shifted to create a perfect match to
                                                                  the FIB image, as depicted in Figure 19.




Figure 17: Digital magnification is used to illustrate CAD
overlay errors. Note that errors may be slightly different in
different parts of the field-of-view.

One solution to this problem is to perform a 3-point re-
registration that stretches, shifts, and/or rotates the CAD
overlay to create a customized match of a particular FIB
image. Note that this is different from the original 3-point
global stage lock that was performed at the beginning of the
edit. The original 3-point global stage lock is a rather coarse   Figure 19: After performing the 3-point re-registration, the
alignment, whereas the 3-point re-registration is a local         CAD overlay is a much better match to the FIB image.
adjustment that is superimposed on the global lock to refine
the accuracy of the overlay.                                      Digital magnification can also be used to position the milling
                                                                  pattern over the target region, as depicted in Figure 20.




                                                                  Figure 20: Digital magnification is used to accurately
                                                                  position milling patterns after the 3-point re-registration.
Figure 18: The user identifies local offsets (3 in this image)
which will be used to re-register the CAD overlay. The black      Because the milling patterns are placed according to the
crosses mark visible features in the FIB image, and the white     custom-stretched CAD overlay, their positional accuracy will
crosses mark the corresponding polygon in the CAD overlay.
be better than what would be achieved from a single reference        and/or increase the refresh time, in order to avoid milling
point. Figure 21 illustrates the accuracy of a typical targeting     instead of depositing. Patience is required.
event using this technique.
                                                                     Third, the large difference in Z height between the top-surface
                                                                     of the silicon and the bottom of the trench requires some
                                                                     adjustments to the FIB hardware. For example, users typically
                                                                     set the top-surface of the silicon to a pre-determined
                                                                     “eucentric” height before beginning an edit. However, on a
                                                                     full-thickness sample this means that the eventual bottom of
                                                                     the backside trench will be considerably lower than this ideal
                                                                     height. The position of gas nozzles may be ill-suited to
                                                                     working at the bottom of the trench. Additionally, the travel
                                                                     range of the IR microscope may not be large enough to image
                                                                     the bottom of the trench. To overcome these challenges, users
                                                                     may wish to position the sample slightly above the normal
                                                                     “eucentric” position prior to beginning the edit.

                                                                     Fourth, some edits are simply not feasible with full-thickness
                                                                     substrates. For example, FIB users are occasionally asked to
                                                                     bring probe pads up to the top surface of the backside silicon.
                                                                     This type of request is challenging even on traditional
                                                                     backside samples (which usually have less than 100 μm of
                                                                     silicon remaining). Performing this task on a full-thickness
                                                                     trench (which is several times deeper and likely to have more
                                                                     textured sidewalls), is probably not worth it. Electrical
Figure 21: Typical targeting result using the 3-point re-            probing is also sometimes performed at the bottom of
registration technique. In this case, the observed beam-             trenches. In such cases, users will need to carefully consider
placement error was 33 nm. The FIB image used for the                the size requirements of the probing hardware, before
targeting event had a horizontal field width of 179 μm.              committing to a full-thickness approach.

The white pattern (labeled #2 in the image) marks the                Fifth, trench planarity and milling speed are sometimes at
expected location of the target (a tungsten contact), based on       odds with each other. For example, under extremely gas-
the 3-point re-registration technique. The actual, observed          enhanced conditions, the material removal rate is maximized,
position of the contact was 33 nm away from the expected             but trench floors are often rounded, with the center deeper
position. Recall that the FIB image that was used for this           than the edges. Conversely, when a trenching process is gas-
targeting event had a horizontal field width of 179 μm.              depleted, it is common to observe that the edges are deeper
                                                                     than the center. Figures 22a and 22b illustrate this
Another advantage of this technique is that it is extremely          phenomenon.
non-invasive. The process can be performed with a single
high-resolution, low-magnification FIB image, and does not           Because speed is an important consideration in full-thickness
require the user to go to live milling to navigate to lock points.   trenching, Silicon-on-Insulator (SOI) substrates are ideal
                                                                     candidates for the full-thickness approach, [12] because they
Other Considerations. After the target has been located, the         tend to be self-planarizing. For example, the FIB operator can
process for completing the edit is similar to traditional            proceed at maximum milling speeds until the buried oxide is
backside CE. However, some unique factors should be                  exposed. The beam is then switched off, but the XeF2 gas is
considered.                                                          allowed to continue flowing over the sample. The remaining
                                                                     silicon will be gradually attacked by the spontaneous nature of
First, secondary electron intensity in the bottom of a full-         reaction (1), and the bottom of the trench will widen,
thickness trench is considerably lower than in standard              increasing the surface area of the work site without eroding
backside trenches. Therefore, the usual techniques that are          the buried oxide.
employed to boost S/N (such as reducing the aspect ratio of
small access holes by using overlapping milling patterns)            Finally, users should consider the economic tradeoffs of the
become even more critical. Visual endpointing may be less            full-thickness approach. FIB tools are expensive, and FIB time
reliable, and other endpointing techniques (such as stage-           is valuable, whereas conventional thinning and polishing
current measurement) may be useful.                                  equipment is relatively cheap. It may not always make good
                                                                     economic sense to use FIB tools to perform long trenching
Second, gas depletion effects can be a problem at the bottom         tasks. As always, the benefits and liabilities of the full-
of full-thickness trenches. Gas-assisted etching processes           thickness approach should be analyzed against the “big-
seem to work fairly well, but depositions can be more                picture” of a particular task. The technique may not be the
difficult. It is often necessary to reduce the beam current
best solution in all cases, but it can be a useful tool to extend   by adjusting the sample height prior to the edit. Although it
the total capabilities of a FIB lab.                                may not be the best approach for every edit, the full-thickness
                                                                    approach should be considered as one of the many options
                                                                    available to the FIB operator.


                                                                                     References and Notes


                                                                    [1] Livengood, R. H., Winer, P., Rao, V. R., “Application of
                                                                        Advanced      Micromachining       Techniques    for    the
                                                                        Characterization and Debug of High Performance
                                                                        Microprocessors,” J. Vac. Sci. Technol. B, 17(1), (1999),
                                                                        pp. 40-43.
                                                                    [2] Lee, R., Antoniou, N., “FIB Micro-Surgery on Flip-Chips
                                                                        from the Backside,” Proc 24th International Symposium
                                                                        for Testing and Failure Analysis, Dallas, TX, November,
                                                                        1998, pp. 455-459.
                                                                    [3] Antoniou, N., “The Process of Editing Circuits Though the
                                                                        Bulk Silicon,” Microelectronics Failure Analysis, Desk
Figure 22a: A backside trench performed under gas-enhanced              Reference, 5th Ed., (2004), pp. 71-75.
conditions (beam current = 21 nA, pattern size = 100x100            [4] Barton, D. L., Cole, E. I. Jr., Bernhard-Höfer, K., “Flip-
μm, loop time = 5.1 msec). Note that the center is deeper than          Chip and ‘Backside’ Sample Preparation Techniques,”
the edges.                                                              Microelectronics Failure Analysis, Desk Reference, 5th
                                                                        Ed., (2004), pp. 42-48.
                                                                    [5] Perungulam, S., Wills, K. S., “Chip Access Techniques,”
                                                                        Microelectronics Failure Analysis, Desk Reference, 5th
                                                                        Ed., (2004), pp. 312-322.
                                                                    [6] Ehrich, D. J., Tsao, J. Y., “A Review of Laser-
                                                                        Microchemical Processing,” J. Vac. Sci. Technol. B1,
                                                                        (1983), 969.
                                                                    [7] Silverman, S., Aucoin, R., Mallatt, J., Ehrlich, D., “Laser
                                                                        Microchemical Technology: New Tools for Flip-Chip
                                                                        Debug and Failure Analysis,” Proc 23rd International
                                                                        Symposium for Testing and Failure Analysis, Santa Clara,
                                                                        CA, 1997, pp. 211-213.
                                                                    [8] Li, Y., “Accurate Predictions of Flip Chip BGA
                                                                        Warpage,” Proceedings 53rd Electronics and Components
                                                                        Technology Conference, 2003, pp. 549-553.
                                                                    [9] Sawada, Y., Harada, K., Fujioka, H., “Study of Package
                                                                        Warp Behavior for High-Performance Flip-Chip BGA,”
                                                                        Microelectronics Reliability, Vol. 43, Issue 3 (2003), pp.
Figure 22b: A backside trench performed under gas-depleted              465-471.
conditions (beam current = 21 nA, pattern size = 100x100
                                                                    [10] S. Herschbein, C. Rue, C. Scrudato, E. Hermann, “FIB
μm, loop time = 558 msec). Note that the edges are deeper
                                                                       Chip Repair: Improving Success by Controlling Beam-
than the center.
                                                                       Induced Damage and Thermal / Mechanical Stress” Proc
                                                                       30th International Symposium for Testing and Failure
                                                                       Analysis”, Worcester, MA, November, 2004.
                        Conclusions                                 [11] Bassom, N., Mai, T., “Modeling and Optimization XeF2-
                                                                       Enhanced FIB Milling of Silicon,” Proc 25th International
Despite the challenges, backside CE on full-thickness silicon          Symposium for Testing and Failure Analysis, Santa Clara,
devices is indeed possible. Modern IR camera technology is             CA, November, 1999, pp. 255-261.
adequate to view circuitry details through many full-thickness      [12] Herschbein, S., Rue, C., Scrudato, C., “The Joy of SOI:
devices. Silicon trenching can be performed in a reasonable            As Viewed from a Backside FIB Perspective,” 31st
amount of time by a combination of high-flux gas delivery              International Symposium for Testing and Failure
hardware and optimized milling parameters. Navigational                Analysis”, San Jose, CA, November, 2005, pp. 78-83.
techniques exist that allow high targeting accuracy without
relying on corner fiducials. Finally, the limitations associated
with gas depletion and IR objective positions can be overcome

				
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