Seamless Electronic Integration - A Proposal for Demonstrator

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					    Seamless Electronic Integration
- KTH Research and Education within EPROPER Program -

                        February 2001

                 Li-Rong Zheng, Hannu Tenhunen
     Department of Microelectronics and Information Technology,
         IT University, Royal Institute of Technology (KTH)
                    {lrzheng, hannu}

Current EPROPER Activities at KTH
Planned Research
Facilities, Collaborations, and Expected Results
Education Activities with EPROPER


         Traditional Multi-Level Packaging Hierarchy




                                       (a) PCB Implementation (silicon efficiency ~5%)

                                                               (b) Conventional Multi-Chip
                                                                Module with bonding wire
              Off-chip signal path !
                                                                (silicon efficiency >25 %)
Chip A                             Chip B
 Bottleneck of Electronic Package: a system view

   Chip A                                          Chip B

                                                  Feature size
                                         Silicon: in um and sub-micron,
Impedance discontinuity,
                                         Packaging: in mm and sub-mm
   Signal integrity,
Simultaneous switching
                                                  Parasitic C L
    noise (SSN)!!!
                                     Silicon: fF, pH; Packaging: PF, nH

                                        Power Consumption                 Silicon Real Estate
              on-chip: ~GHz,
                                      core: ~(50%-70%)Ptotal          logic core: ~(50%-70%),
             off-chip: <500M
                                  off-chip driver: ~(30-50%)Ptotal   off-chip driver: ~(30%~50)
            system: <300 MHz

                                                                     Extra silicon area for
             Degraded off-chip/   Extra power consumption for
                                                                     large off-chip driver;
            system performance           off-chip driver;
                                                                         Cost, size etc.
                                   Thermal, mechanical etc.
 Bottleneck of Multi-Level Package: Summary

Power Consumption: in a modem microprocessor, 60~70% total power consumed on global
buses, I/Os, clock distribution

Simultaneous Switching Noise [Ldi/dt]: in a 80W 2.5V CPU chip, di/dt= 64GA/s. If a
package pin has a typical Lpin=1nH and DVmax< 10%Vdd , the required number of power I/O
pins will be >256 !!!

Degraded Off-Chip Speed: On-chip speed of a CPU chip is in GHz, off-chip <200MHz!

Signal Integrity: Impedance Discontinuity, Package pins behave like low-pass filters and
stop the high frequency signals

Expensive Chip Area: Many chips are package pin limited due to large size of bonding pads,
very larger off-chip drivers also occupy a large amount chip area. Typical area: 30~50% for
I/Os, and 50~70% for logic cores

“The Ultimate Electronic Package Configuration will be the
Disappearance of Package !!!”
-- Nasser Greyali, Director of Assembly Technology Development, Intel Corp, (Oct. 2000)

       Source: PHILIPS with some modification according to ITRS’99                        Seamless
       (Internal Technology Roadmap for Semiconductors, 1999 Edition   )                  Integration

                                                                                    System-in -
                                                                                    Package (SiP)

It’s not just a shrink in size, and more important, it provides:

 • Very High Performance
 (shorter chip-to-chip interconnections, and reduced parasitic
 effects e.g. Lpin =5nH in PLCC and Lpin =9pH in flip-chip)

 • Broadband
 (Shorter chip-to-chip interconnections and better impedance
 control, higher I/O pin count, higher data throughput per pin )

 • Mixed-Signal Integration
 (e.g. Digital /analog/RF, silicon/SiGe/GaAs technologies )

 • Lower Power
 (save power 10~50% !, due to reduced off-chip driver
 requirements )

 • Others
 Reduce Cost: save expensive chip real-estate by reducing off-
 chip drivers:
 Lower Switching Noise (Ldi/dt): e.g. Lpin =5nH in PLCC pin
 Lpin =9pH in flip-chip bump
                                                                   From TH-PCB package to SMT-PCB
 Applications:                                                     package to MCM integration
 Mobile terminals, communication links, PDA, and high-
 performance computers

 Seamless Electronic Integration Means:
  • Technically, to close the gap between packaging chip, such that we are able
    to achieve orders of magnitude improvements in size, cost, functionality, and
    overall system performance, as well as low power
  • Physically, to develop an integrated unified electronic system that is
    optimized by efficient chip/ packaging/ system co-design with considerations
    of electrical/ thermal/ thermo-mechanical effects in a self-consistent manner

  • e.g. Single-Level system-in-package integration (chip-first, chip-last), silicon-on-silicon,
    wafer-level package with embedded passive components and/or thin chips
  • Key Fundamental Technologies: flip-chip technology, single-level chip integration,
    embedded passive elements, microfabrications

From chip/system design perspective, it is really necessary to integrate future
electronic systems towards seamless integration. This we can see a similar
transition as going from discrete devices to integrated circuits and we expect, if
this transition is successful, a similar impact on electronics as the integrated
circuit has had up to today

Seamless Electronic Integration: example (GIT, Atlanta)

   SLIM: A chips-last system integration approach which is under cultivating at
           Packaging Research Center, Georgia Institute of Technology

Seamless Electronic Integration: example
                              (Fraunhofer Institute, Berlin )

      Thin chip integration has ultrathin chips integrated in the
      redistribution layer of a larger chip. (Source: Fraunhofer IZM)

   Seamless Electronic Integration: example (KTH, Stockholm)

   Single-Level Integrated Packaging (SLIP) -- an extension of VLSI technology



                                                                      DSP               Control Unit

                                                                            off-chip interconnect layer
                               I/O                                           Unique Features:
                                                                             • IC backend Process
                                                Power and Ground             • Ultra high package density
                                                Distribution Layers          • Mixed signal integration
 Dielectric(                                    Signal Wiring Layers         • High performance
 SiO2, low
                                                                             • Good pad driver capability
                 Substrate                                                   • Low power
                                     chip                                    • Weight, size, cost etc

SLIP - a chips-first seamless electronic integration approach being under development at KTH.
  Test samples have been made during 1999~2000 (using VLSI process + low k dielectrics)
Current Research Activities

 Research Activities: single-level integration packaging

  Process Sequence for SLIP: with VLSI Processes

          sample holder
                                                   sample holder

                                                                                         (c) Polyimide cure and
     (a) Back surface polishing              (b) Substrate bonding                       sample holder removal

(d) Multi-layered silica xerogel         (e) RIE via-hole etching and contact-            (f) Metal film deposition and
  deposition and planarization                       via deposition                        interconnect pattern

                              chips                                              polyimide

                              vias                 Al metal                      Silicaxerogel


        SLIP fabrication steps. Repeating steps (d) to (f) makes multi-layered interconnections
 Planarization Technique: Multi-Layered Spin-on Coating

                                         (a) after 1 layer coating    (b) after 5 layers coating

Precursor: TEOS + water
Solvent: Ethanol
Spin rate: 1000~5000rpm
Cure: 350~400oC 15min
                                         (c) after 8 layers coating    (d) after 10 layers coating
Number of layers: 10
                                                                             and metallization
Total thickness ~ 10mm
r=2.2, tan()= 0.02 @1MHz   Top surface view of the module after multilayered spin-on coating planarization.

Test modules for Single-level Integrated Package

                            5 mm
               chip 1
                   chip 2   chip 3                       5 mm
                                                    chip 1

                chip 4      chip 5
                                                chip 2    chip 3
                chip 6      chip 7
                                                chip 4   chip 5

               chip 8       chip 9
                                                     chip 6

                         (a)                       (b)
         Photos of tested samples of single level integrated packaging
        modules with 9 individual chips (a) and 6 individual chips (b),

HF Properties of Package and Interconnects :Modeling & Measurement

                                                                                                                             HP 8510A (45M-20GHz)
                                                                                                                             On-chip G-S-G probe
                                                                                                                             SOLT calibration,
                                                                                                                             Y-parameter de-embed of pads

  Example scattering parameter measurements and model simulations of two 10 mm wide 0.7cm
 long interconnect wires separated by 10 mm, where S11 is associated with input reflection, S13 is
 associated with transmission, and S14 is associated with far-end coupling. Solid line: simulation
 data, dot line: measured data. : start frequency (45 MHz), Δ : stop frequency (20 GHz).

                                                                            )
                                                             S t  T Z *  Z t  ST (Z  Z t )    T Z
                                                                                                 1        *
                                                                                                                    )               
                                                                                                                Z t*  ST (Z  Z t* ) (5)
                                                             S: the original scattering matrix referenced to Zk at port k
Reference Impedance Transformation:                          St: the wanted scattering matrix referenced to a new impedance Ztk at each port k (k=1,2,3…2N)
                                                                        1 
                                                             T  diag             , Rk  Re(Z k ), Rtk  Re(Z tk )
                                                                        Rk R tk 
                                                                                  
                                                             Z  diagZ k , Z t  diagZ tk , k  1,2,...2 N
                                                             and with Z* the complex conjugate of the impedance matrix Z.
   Research Activities
l Interconnect Parasitic Extraction                             Tools: FEM, FDTD, MoM, and PEEC

 q 3(2)D Numerical Simulation                                                                                
                                                                                                 2 A jm A   m J

 Accuracte, Time and memory consuming,
                                                                                                         
 Inefficient for full chip extraction                                                           B   A
                                                                                                      on       strip1
                                                                                                     J
                                                                                                J   J 0 on substrate
                                                                                                     0       others
                                                                                                  Neumann boundary
                                                                                                 conditions at metal and
                                                                                                     substrate edges
                                                                                                The equation is solved by
                                                                                                 Finite Element Method

                          Figure: 3D Interconnect
                     Capacitance Extraction for an                                      
                                                                                  1  j
                                                                                                0
                                                                                          0 
                                      SRAM Cell
                                                                                  wt       
     ˆˆ            ˆ   ˆ                             Z k  )  Rk  )  jLi  
     LC0   0 m 0 I  L                                                            1  j )   
                                                                                  wt  0             0
A Parameterized Interconnect Model

   Technology             Wire parameter: w, d,
  description file           metal layer etc

              2D field solver:
                 Cm, Cg

                                                1                                  Cm
   Curve fitting:                     h                                                       d       w           h
                      C 'f  C f 1  ( )  
                                      d 
            Empirical formula:                                       Cf Cp C f ’ Cf ’ Cp Cf ’ Cf ’ Cp
          Cm, Cf, Cf’,  ~F( w,d,h,t)                                             Cf
                                                                                                       w     t
                                                                                                                    0.222 
                                                                                                                                            h 
                                                          Cg    C f  C p  C 'f   , C f   k 0.075    1.4        , C f  C f 1  ( ) 

                                                                                                      h      h       
                                                                                                                                           d 
                3D capacitance                                       w              ww        
                                                          C p   k  , Ccross   k  1 2
                                                                                       h          C f 1 2  C 'f 1 2  C f 21  C 'f 2 1
                                                                    h                1 2     
                                                                                     w      t      t
                                                                                                          0.222 
            Inductance extraction                         Cm  C f  C 'f   k 0.03   0.83  0.07         
                                                                                    h       h      h        d 
            ˆˆ            ˆ   ˆ
            LC0   0 m 0 I  L
                                                                                        
                                                                                  1  j       0
                                                                                  wt    0 
         Skin effect resistance                      Z k  )  Rk  )  jLi            
                                                                                    1  j )   
                                                                                  wt  0             0
                                                                                                                                                 19
Power Distribution and Synthesis

             Lp            Vdd

              on                                            Vin

         Lp                Vss

        Le                       Lp
                   Vp-1                     Vp
pwr                                   Vdd
                          Rp=2Rw            Ip

                                 Cp         Switchin
                   Z=p-1                     g Core

 • L.-R. Zheng: Efficient and Accurate Modeling of Power Supply Noise on
 Distributed LRC On-Chip Power Network, IEEE ISCAS 2000
             Why power distribution? -- a packaged system view

                                                                 System level power
                                                                  delivery network

                                                                 High-Frequency on-chip
Impedance                                                      global and semi-global lines

  0.025                                                 Chip on SCM/MCM

  0.015     1999 Target                               Mid-Frequency
            Impedance                               SCM/MCM on Board
  0.010                         Low-Frequency
                                Power Regulator
      100     101         102    103     104      105    106      107     108    109     1010
                                         Frequency (Hz)
     Packaged ULSI Power Distribution: Challenges

                                                A capacitor chip is
                                                bonded to an Alpha
                                                21264 processor chip
                                                to provide power

Extremely large size of the network
 • Millions and hundreds millions of nodes typically,    SPICE simulation: >>3 months

Complex structures
     • Topologies: meshes, trees, rings, planes,   I/O distribution: peripheral edge, area array connection etc
Many unknowns at early design stages
     • Decision about structure, size, layout, and package parameters must be made at early stage
     • Parasitic, current profile of each block are not known until very end of the design cycle

Problems revealed at post-layout stage are expensive to fix
Design of on-chip decoupling capacitor is complex
Equivalent Circuit Model of Power Grid

                                                  Rp-1,p       Lp-1,p
                                           Vp-1                           Vp
                 p-1    p

        Modeling of a meshed power grid with a chain of p-type equivalent circuits.

 CLp: switching load capacitance(clock cycle dependent) , extracted from gate level power
        with Cw,p: wire self capacitance
             Cm,p: mutual capacitance between Vdd and Vss
             Cqp: sum of load capacitance of quiet gates (symbiotic bypass capacitance)

Peak Noise Formulation for an Arbitrary Node in an Arbitrary Grid

             Vk                                     V4
                                                                     CT = 0.5(C1,j + C2,j + C3,j +…+ Ck,j).
                                                                            CLj: switching capacitance at node j

Basic idea: switching charge                                    CT Vdd  Q  (CT  C Lj )V pmin

                            k                        k                          k

                                                                               
        Q                           I ( ) d            i , jVi V j              i, j    i , j  t 2 (6Li , j  3Ri , j t f )
                                                                     min  min
                            i 1,i  j i 
                                            
                  0                                                                                         f
                                                   i 1,i  j                 i 1,i  j

                                              1 k
                               V     min
                                               Ci , jVdd                                                                  k
                                                                                                                                              1 k
                                                                     1                                         j                             
                            i, j i
                                              2 i 1,i  j                    k                  k
                                                                                                                                                        Ci , j  C Lj
  V jmin 
             i 1,i  j
                                                                           i , jVi min  1  Ci , jVdd                          i, j
                                                                                                                                              2 i 1,i  j
                   k                           k
                                                                      j  i 1,i  j                                  i 1,i  j

                                               Ci, j  CLj
                                           1                                                2 i 1,i  j  
                                i, j   
              i 1,i  j                   2 i 1,i  j

  Peak Noise Formulation for Arbitrary Power Grid

We can write the noise equation (with total n nodes) in matrix form as:                                      m
                                                                                           i    j            m+1
          12     13      1m        1n                 n
                                                               Ci ,1Vdd 
                                                                       
  1                            
                                       1 
          1      1        1               min      i  2 21                   4    5     6
   21            23      2m        2 n  V1            Ci , 2Vdd 

          1                                 min                    
  2             2       2         2  V2   i 1,i  2 22                   1     2    3
         32              3m        3n  V3min   n Ci ,3Vdd 
                                      3       i  3 23 
  31             1                                 
  3      3               3                       1,i                  Free (unknown potential )
                                                                        
                                      min                         nodes:    1,2,3,…m-1,m
   m1    m2     m3                 mn  Vm   n Ci , mVdd 
                                      m      i m 2m 
                       1                           
  m     m      m
                                           Vn  
                                                          1, 
                                                                      Prescribed (fixed potential)
                                                                      
   n1    n2     n3    nm                            n 1
                                                               Ci , nVdd     nodes:     m+1,m+2, n
                                      1              
                                                        2 n 
                               
  n      n      n     n                           i 1              

   Or in a submatrix form as

    φf f        φ f p   Vf  b f                 Vf  V1 V2 V3  Vm 

    φ                         
     pf         φ pp  Vp  b p 
                                               Vp  Vm1 Vm 2  Vn1 Vn 

Concurrent Design Example: Decoupling Capacitor Design

    Package inductance         2pF decaps
                                                                             before decap
   Sketch of a 10 by 10 power grid with four
   external supply connections. X: 150mm/grid,
   Y: 100mm/grid

                                                                                    after decap

    Comparison of peak noise before and after decoupling
    capacitors placement.

    CPU time: in our tool is 0.06 second , whereas in HSPICE it takes >25 seconds                 26
        Self-Decoupling Power Distribution


                                        Vdd   Vss

                                        Simplified sketch of on-chip power distribution

                                    Output impedance of power
                                    lines with various cross
                                    sections and line lengths.
Impedance (ohm)


                                                        One fat Vdd-Gnd pair with
                                                        w=64mm, d=48mm

                                                        40 small Vdd-Gnd pairs
                                                        with w=1.6mm, d=1.2mm

                  Frequency (Hz)
Power Distribution & On-Chip Decoupling

                                                       • Area Array Connection
                                                       Power/Ground Pin
                                                       Distribution for External
                                                       • Self-Decoupling between
                                                       Vdd and Gnd
  Vdd pins              Vss pins

         o Vn=150mV
         * Vn=300mV
                                                  An example of required minimum
                                          f=20%   number of power/ground pin pairs in
                                                  per cm2 chip area as a function line
                                                  pitch width for power distribution,
                                      f=10%       where Vn represents allowable noise
                                                  margin and f represents a switching
                                                  factor in the chip.
             average current constraint

Current Research Activities @KTH (summary)
Single level integrated packaging module study
        Material deposition, Spin-on coating, Planarization technique,
        Metallization and Interconnection pattern by life-off process
        Electrical design, modeling and measurement (45MHz~20GHz)

Mixed-signal coupling and digital signal integrity
        3D full wave analysis of interconnection and package
        HF Interconnect measurement and modeling from measurement
        Interconnect delay and crosstalk analysis under deep submicron constraint

Power distribution and on-chip decoupling strategy research
        Unified chip/package irregular power grid modeling and simulation
        Nose reduced power distribution with self-decoupling and area array I/O
        Chip/package co-simulation for power distribution and signal distribution

Passive devices and effective antenna (smart antenna structure)
for compact systems
        Target to mixed-signal integration with digital and analog/RF

Publications in 2000
(1) Li-Rong Zheng, Hannu Tenhunen:
    “Single Level Integrated packaging Modules for High Performance Electronic Systems, ” in proc IEEE 50th Electronic
    Components and Technology Conference, pp.1460-1466, 2000 and was invited to submit to IEEE Trans. Advanced
    Packaging for a Special Issue
(2) L. R. Zheng and H. Tenhunen.
    “Fast modeling of core switching noise on distributed LRC power grid,” in Proc. IEEE 2000 Electrical Performance of
    Electronic Package Meeting, Scottsdale, Arizona, USA, Oct. 2000 and was invited to submit to IEEE Trans Advanced
    Packaging for a Special Issue.
(3) L.-R. Zheng and H. Tenhunen.
   “Single level integration packaging: meeting the requirements of ultra-high density & high frequency,” accepted by Journal of
    Electronics Manufacturing, 2000
(4) Li-Rong Zheng, Bingxin Li, Hannu Tenhunen:
    “Efficient and Accurate Modeling of Power Supply Noise on Distributed On-chip Power Networks”, in proc IEEE
    International Symposium on Circuit and System, pp.II 513-516, 2000
(5) Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen:
   “Accurate A Priori Signal Integrity Estimation Using A Multilevel Dynamic Interconnect Model for Deep Submicron VLSI
    Design” in Proc 26th European Solid-State Circuit Conference, Stockholm, Sweden, Sept, 2000
(6) L. R. Zheng and H. Tenhunen.
    “Design and analysis of power integrity in DSM SoC circuits,” in Proc. IEEE 2000 Norchip Conference, Turku, Finland,
(7) Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen:
    “Combating Digital Noise in High Speed ULSI Circuits Using Binary BCH Encoding” in Proc. IEEE International
    Symposium on Circuit and System (ISCAS’2000), pp.IV.13-16, 2000
(8)Bing-Xin Li, Li-Rong Zheng, and Hannu Tenhunen
   “An Improved Settling Model of Swithed-Capacitor Integrator for High Speed Sigma-Delta Modulator Simulation,” in Proc.
    IEEJ 2000 (4th) International Analog VLSI Workshop, June 2-3, 2000, Stockholm, Sweden
(9) L.-R. Zheng, and H. Tenhunen, “Efficient modeling, analysis and design of power grid for CMOS ULSI circuits ” submitted to
    IEEE/ACM Design Automation Conference, Las Vegas, 2001
(10) L. R. Zheng and H. Tenhunen
    “Global interconnect design for high speed ULSI and SoC,” presented in EDA-Traff 2000, Design Automation Conference,
    Kista, Stockholm, Sweden, April 2000.
Planned Research Focus and Research Team

  KTH's Focus
 Seamless Integration Technology
  • Wafer-Level Packaging with Embedded Passive Components
  • Single Level Integrated Packaging Modules
  • Aims of experimental work mainly are
      (a) experimental verification of simulations
      (b) “extension” silicon technology to package technology

Seamless Modeling and Simulations for the Package Modules
    • Chip/Package/System co-design and simulation
    embedded passive elements, unified chip-package interconnection modeling, seamless on-chip and off-chip routing, novel
    circuit and system architectures with seamless technologies for clock and power distribution, system buses, high speed and low
    power off-chip signaling techniques, system partitioning and system timing, with emphasis on early estimation

    • Mixed-signal coupling and digital signal integrity
    • Unified electro-thermal modeling and measurement

 Importance of Future Passives Integration

       In RF Circuits                          In Digital Circuits

                                            The number of passives is significant in
                                            digital (non-RF) circuits, especially for
This chart (made available from             the suppression of line noise and
Nokia) illustrate the decrease in ICs       electromagnetic interference (EMI)
and passives in the RF section of a
GSM phone from 1994 to 2000
                                        Source: Wireless System Design, Feb. 2000

 KTH Focus 1: Seamless Integration Technology
 1. Wafer-level packaging with passive components and optimized
    seamless off-chip interconnections for long on-chip communications
     Decoupling Capacitor     High-Q Inductance

                                                                        Dielectrics (10~20mm)
                                                                    Passive dielectric (1~2mm)

              Global interconnections
                                             Silicon chip
              (on-chip) ( off-chip)

2. Single Level Integrated Packaging Module: continue our previous research, with
   emphasis on embedded RF components and applications such as in a Bluetooth
   Module and Wireless LAN (WLAN) module.
    Decoupling Capacitor High-Q Inductance
                                                                          Power distribution

                                                                          Signal distribution
              RF IC         Digital IC    Digital IC        Analog IC      Dielectrics (10~20mm)

        Focus 2: Seamless Modeling and Simulations
  The aim of this study is mainly to find out the impact of package parasitic effects on
       • (1) Signal transmission and signal integrity;
       • (2) System-timing and system performance;
       • (3) Chip I/O design and power distribution;
  and hence
       • (4) Optimized system partitioning and system performance
                                                                           VCO       Loop
                         DSP      PCI     Timer     ROM        RAM
                         RISC       Ethernet       Memory       API       ASIC      Balun
                         MPU       Controller     Controller
                                                                SSP      Switch Antenna
                         bridge     UART Watchdog                        Custom modules
                                    IP modules                           RF components

                                    SSP    DSP RAM             RISC    Memory      Antenna
                                                               MPU    Controller    Filter
                                    SSP     API    ROM
                                                                       Ethernet    Switch
System-in-package design          PCI                                 Controller
example: co-simulation and                         bridge             Balun        VCO
system partitioning                                                    Radio       Loop
                                  UART      Timer      Watchdog        ASIC        filter

Aim of the Project
Key technologies for seamless integration is emerging or has emerged,
aim of this study:

• Bring a new view of system integration (other than an incremental technology
  improvements) that enables new levels of integration both in system complexity and
  in technology fusion;

• Evaluation of the new technologies (both challenges and opportunities) for
  seamless integration systems, with regard to integration density, thermal
  characteristics, electrical performance, signal integrity, and particular applications;

• “Extension” of silicon technology to package technology for seamless integration;

• New design space exploration for such integrated systems in a unified chip-
  package-system co-design manner with emphasis on high performance systems and
  efficient design techniques.

        KTH’s New Team in EPROPER
                                Supervisor:                             Co-Supervisor:
                         Prof. Hannu Tenhunen                     Prof. Mikael Östling,
                          Electronic System Design               Electronic Device Technology

                           Senior Researcher:                                Senior Researcher:

                          Li-Rong Zheng                                Carl-Mikael Zetterling
                     (Start from 05/01) Background:                Background:
                Package and Mixed-Signal System Design,            Power Electronics, RF and HF
                   Material and Thin Film Technology               VLSI and Thin Film Technology

    Ph.D. Student:                Ph.D. Student:                   Ph.D. Student:                       Ph.D. Student:
Mr.Wim Michielsen              Mr. Meigen Shen                 Mr.Xinzhong Duo                          Ms. Wei Liu
                             From Eastcom Ltd. (05/01)       From Osaka University, Japan
EPROPER student(99/00)                                                                            student at EKT, background
                              4y industrial experience in   (05/01) 4y research experience
  Industrial student        communication system design         in thin film and devices          in transient thermal modeling
      (00/01-)                                                 (silicon-silicon bonding )            of combustion processes

                           Seamless modeling and               Transmission line        Thermal and electro-
  Bluetooth Radio            simulation, system/             modeling, EMC/EMI,      thermal modeling, thermal
  RF components            package/ chip co-design,         Material and processing,     measurement and
                               signal integrity             electrical measurement          verification

             (Seamless Electronic Integration) /(System-in-Package)/ (e.g. Bluetooth/WLAN)                                 37
     Student Projects

1. Wafer-Level Packaging and Single Level Integrated Packaging Modules
  for High-Frequency Wireless Communication Devices
        Research Content: subject 1, part of subject 2
                          Senior Reseracher: Li-Rong Zheng, Carl-Mikael Zetterling,
                          Ph.D. Student Xinzhong Duo, ESK/KTH

2. Concurrent Packaging and VLSI Design for High-Frequency Circuits and Systems
        Research Content: subject 3, part of subject 2
                          Senior Researcher: Li-Rong Zheng
                          Ph.D. Student: Meigen Shen, ESK/KTH

3. Unified transient thermal modeling of heat dissipation in high performance electronics
          Research Content: subject 4, part of subject 3
                            Senior Researcher: Carl-Mikael Zetterling, Li-Rong Zheng,
                            Ph.D. student: WEI LIU

Research Subjects:
       1. Seamless package and integration technologies and experimental verifications

 Wafer level packaging (WLP), single level integration package (SLIP) technologies (System-level and mixed-signal
  package, with digital, analog, and RF together), with emphasis on embedded components such as decoupling capacitors,
  integrated inductance, and embedded antenna in WLP and/or SLIP
 Novel materials, substrates, and metallization technology and their high frequency characteristics
 Seamless on-chip and off-chip interconnection technology such as in WLP and SLIP for global on-chip communication,
  area array connection
 High frequency measurement and experimental verification for design and simulations

       2. Signal transmission and signal integrity analysis

 Impact of deep submicon chips on signal integrity issues for packaging and board
 Mixed-signal coupling issues for system-in-package and system-on-chip package
 Electromagnetic full-wave simulation of broadband interconnections, interconnect parasitic extraction, passive
  components modeling and experimental verification
 Effect of impedance discontinuity on off-chip signal transmission and coupling
 Novel high-speed and low power off-chip signaling techniques and their opportunity in seamless integration
 Power delivery, power impedance control and on-chip/off-chip decoupling design
 High-speed data bus design for seamless chip-board communication, high-speed signal distribution
 EMC and EMI problems for package and system
 Signal integrity measurement and model development based on measurement
 Noise rejection techniques and noise measurement
 Based on the above studies, develop a unified 3D interconnect modeling or library from chip to package to board-level

   Research Subjects: (continue)
               3. Concurrent packaging and VLSI/ULSI design

 Performance analysis for system-in-packaging and system-on-chip integration, system level view of integrated chip,
  package, and substrate needs analysis
    (Impact package on chip performance and cost, chip area, power consumption, off-chip speed etc, early stage system
    estimation including packaging effect)
 System-level power distribution strategy, power delivery (board, package, and on-chip) analysis and co-design.
    (e.g. early stage estimation of power/ground pin number, power noise estimation, pin assignment, area array power
    connection or peripheral connection, power impedance control, decoupling design)
 System-level clock distribution strategy with emphasis on GHz on-chip and off-chip
    (e.g. new clock distribution topology and technology such as skewless clock distribution with standing waves,
    distribution on-chip clock using off-chip interconnections and/or clock chips in a package module etc.)
 System-level signal distribution analysis and chip/package/system co-design
    (e.g. using high speed off-chip interconnections to replace long on-chip global wires )
 Thermal management for clock and power distribution with unified chip-package model, system-level electrical-
  thermal co- simulation
    (thermal heating and thermal transient, 3D thermal distribution, impact of thermal effect on power distribution of the
    system )

               4. Unified transient thermal modeling of heat dissipation and transfer

 Heater generation and self heating modeling in semiconductor chips
 3D physical simulation of heat dissipation and spreading in package module (spatial domain), thermal transient
  simulation (time domain), and impact of metal wires on these properties
 High-level and early stage seamless electrical-thermal co-simulation, e.g. thermal simulation with high-level hardware
  description language such as VHDL as input
 Modeling verification and electrical-thermal measurement
 Development of high resolution thermal imaging system for thermal mapping in package and chips

Application Area:

For example, highly miniaturized and high performance
electronic systems such as short distance communication
based appliances and personal devices

       Blutooth module: Ericsson

   module: Intarsial               2.4GHz VCO:
Facilities, collaboration, and expected Results

  Equipment & Facilities
Software Program:
• 3D full wave electromagnetic simulation (HFSS), HP-moment (HP-Ads) etc.
• Full license from Mentor Graphic (including package and PCB design, Interconnect Synthesis, IS,
  high-level design and synthesis tools)
• A number of other circuit and system simulation-tools from such as Agilent, Cadence,
  Synopsys (a complete set of CAD tools from system-level, gate-level, transistor-level, and layout-level
• Several in-house developed tools and algorithms (LRC extract, power distribution, interconnect
  post-processing, system-level interconnect simulation etc.)
• Device and process simulation tools from Avant!, Silvaco and ISE, which allows electrical,
 magnetic and thermal simulations in 2D and 3D ( External circuits are also possible)
•Several HP network-analyzers (20GHz and 60GHz), probe station, TDR(20GHz)
measurement, BER measurement, DC (20fA, 1mV)
•Thermal imaging system is going to be set up by other students at EKT
•KTH clean room with full access collaborated with EKT
KTH Clean Room
•Equipped with a complete line of facilities for semiconductor processing, package and
assembly, providing for research projects in KTH and ACREO. (e.g. various facilities for thin film
deposition and lithography, thermal processing, device mounting, and flip-chip bonding)

Electrical Characterization, EKT/KTH

KTH Facilities (example)

      PECVD           RIE             Sputtering

     Evaporator       Lithography     furnace

         spin          polish       Wet chemical

  Our specialized competence (summary):
Very Experienced in Chip and System Design
Currently working on: system-level, algorithmic level, logic level, circuit-level, and physical level designs
Most of research projects are currently going with these different design levels, with focus on system-on-chip,
mixed-signal systems, ADC/DACs, DSP, Low Power ICs, High Speed CMOS ICs, and RF ICs.

Competence in Modeling and Simulation of Electronic Package
LRC parasitic extraction with full wave analysis ( FEM, FDTD, MoM, PEEC)
Professional CAD platforms and a design team consisting of physical level, circuit level, logic level, chip-
level, package and system level
Knowledge in advanced signaling standard, system buses, logic families, signal integrity and system timing
issues, signal and power distribution

Skills in Silicon Technology and HF Electrical Measurements
A complete set of silicon processing line for research, from material deposition and photolithography, to package and
Facilities and expertise in electrical measurement (Scattering parameters, TDR, BER, current in 20fA, Voltage in uV)

With MH:
    • Verification of designs with different simulation tools
    • Test structures implemented in our Silicon Technology
    • Electrical measurements
With CTH:
    • Electrical performance characterization for CTH’s substrate and interconnect materials,
    • Test CTH’s solder bumps in our WLP and SLIP modules
    • Thermal modeling and thermal measurement
With LiTH:
   • Simulation and measurements of electrical performance of interconnections and
     passive components using LiTH’s dielectrics and conductive materials
   • Performance and cost analysis for system-in-package and system-on-chip
   • Effects of non-linearity of dielectrics on signal propagation and signal coupling
   • We can also assist LiTH in device and circuit design in polymer electronics
And more:
   • Particular interests from other University are very welcome
   • Aim is to combine the specialized competence for each university and share the
   facilities, in order to achieve high-quality research and education
   • EPROPER research workshop could be arranged, more possible collaboration can
   be discussed between EPROPER students and researchers
Education Activities

 EPROPER Graduate School

EPROPER Courses at KTH :

•Electronic System Packaging, 5c (SoC Master)
•Digital System Engineering, 5c (undergraduate students)
•Mixed-Signal System Design, 5c (2B5457)
•Physical Architecture Design for VLSI System, 5c (2B5456)

Objective: New competence profiles needed for EE

    Computer                   Signal
   engineering               processing
                                                        and physical
                                                        and physical
  and operating                 and
                                                        ULSI design
                                                         ULSI design
    systems                 communication

 • Deep sub-micron effects require that future chip and system designer/team
   has knowledge on physical level design issues
 • The increasing complexity of electronic systems and system noise problems
   require to explore new design space with unified
   physical/functional/methodology views.

 Challenge: New breed of students than our generations

   Different abstraction views in KTH graduate curriculum in EE

• Physical/Implementation View                                      Methodology view
  where the relevant features of
                                                  Physical      Concurrent Engineering   Functional
  technology are handled at different
                                                  view          Anatomy of EDA Tools     view
  abstraction levels.

                                           Mixed Signal                                    SoC Architectures
• Functional View                          System                    Sys tem
                                           Design                                          Embedded Software
  where the proper abstract
                                                                                          Embedded Systems
  architectures and interfaces between
  different architectural elements are     Digital
                                           System                  Arch itecture
  explored.                                                                                Design Methods
                                                                                               for SoC
• Methodology View                         Circuit
                                                                   Hardware System
                                                                   Modeling                  Digital Design
  where the supporting design
  processes and organizational work
                                                          Basic courses in Electronics
  flows, such as concurrent
  engineering, is covered for efficient   Semiconductor            Analog                Digital
                                          Components               Electronics           Electonics
  and high quality execution of the
  design tasks.

Program Example: Master Program for System-on-Chip

    Course Example: Mixed-Signal System Design

•   Technology foundation (30 %)
     – Introduction to microelectronics packaging hierarchies, interconnectivity and Rent’s rule
     – Core packing and substrate technologies with emphasis on state-of-the-art
     – Thermal design and management
•   Mixed signal design (50 %)
     – Interconnection and substrate models. Impact of inductance.
     – Crosstalk and noise coupling mechanism
     – Fundamentals of EMC at package and board level
     – Chip-package interactions (e.g. Substrate noise) for mixed signal Ics
     – Power and clock distribution
•   Trade-off analysis and conceptual design (20 %)
     – Conceptual design ideas and principles (early/a priori estimates and analysis)
     – Performance and system models
     – Cost models

    Mixed signal system design: technology foundation
•   We review the packaging technology          •   Interconnect substrate technologies
    evolution and outline the future trends         are reviewed. The key interconnect
    and challenges for the chip packaging           technologies on silicon, PCBs and
    and interconnect substrate technologies.        build-up multilayer (BUM) boards, and
•   Functional       requirements         for       different MCM technologies are
    interconnect       are      qualitatively       reviewed and practical integration
    introduced via Rent’s law and                   examples are shown. The emphasis is
    calculation    techniques      for    the       on the key design parameters and
    requirements in interconnectivity are           technology limitations.
    established.                                •   Thermal      design     and    thermal
•   Core technologies for single chip               management for the chip package and
    packages such as wire bonding, TAB,             interconnect substrate technologies are
    and solder pump chip connections are            described. Simple models for thermal
    established. Based on the geometrical           flow and practical examples from PC
    features, equivalent electrical models          and      workstation     domain     are
    for the package are established and few         demonstrated.
    typical packages are analyzed closer.
    The major emphasis is on the current
    BGA technologies and on the different
    chip-scale package technologies.
        Mixed signal system design: performance design
•   We describe the different electrical        •   Power      and      clock    distribution
    design aspects for interconnect                 problems on the PCB and MCM
    substrates. The importance of the               interconnect substrates are described
    inductive terms is emphasized. Key              and different techniques for the problem
    features for high-speed designs are             mitigation are introduced.
    introduced. The common mode and             •   EMI/EMC fundamentals for the
    differential mode radiation and EM field        interconnect substrates and connectors
    patterns from the interconnects are             are described from the first principle
    reviewed. For these phenomena, the              point of view.
    equivalent circuit models are given for     •   Interconnect layer stack strategies for
    analytical or Spice based analysis.             the signal integrity and minimal
•   Pulse propagation and signal integrity          EMI/EMC disturbances are reviewed
    are described with emphasis on the              for multilayer interconnect substrates.
    transmission line effects and on                Floorplanning and layout techniques for
    interconnect substrate structures.              the mixed signal and high signal
    Different impedance discontinuity               integrity designs are introduced and
    mechanisms on the interconnect                  analyzed beyond simple "rule of
    substrates are described. Coupled               thumb".
    transmission line model for the crosstalk   •   Interaction of the chip package and
    between the interconnect lines is               the chip are described in areas of the
    introduced. Different techniques for the        simultaneous switching noise, power
    crosstalk and reflection minimization are       distribution and substrate noise
    introduced.                                     coupling issues for the high speed
                                                    and/or mixed signal VLSI circuits.
            List of lecture content/course material

Chapter 1      Design and technology evolution of            113 pages
               electronic systems from chips to cabinets
Chapter 2      Interconnectivity analysis and Rent’s rule:   98 pages
               A functional view to packaging
Chapter 3      Single chip packaging                         138 pages
Chapter 4      Ball grid array and chip size packaging       114 pages
Chapter 5      Interconnects on silicon                      169 pages
Chapter 6      Interconnect substrate technologies:          122 pages
               PCB & BUM
Chapter 7      Interconnect substrate technologies for       154 pages
               multichip modules and MCM design
Chapter 8      Electrical design aspects for interconnect    146 pages
               substrates at high frequencies

             List of lecture content/course material

Chapter 9      Interconnect models for transmission lines        128 pages
Chapter 10     Coupled interconnections and transmission lines   108 pages

Chapter 11     Noise mechanism on interconnect substrates        130 pages
Chapter 12      Mixed signal design for interconnect             113 pages
Chapter 13      Simultaneous switching noise in ICs              50 pages
Chapter 14     Mixed signal coupling in ICs                      158 pages
Chapter 15     Thermal management                                61 pages
Chapter 16      Performance modeling and conceptual              58 pages
Chapter 17     System partitioning and tiled silicon             68 pages
Chapter 18     Trade-off analysis for MCMs                       120 pages

Expected Long Term Results

• Knowledge on material and process for Wafer-Level Packaging (WLP) and Single-
 Level Integrated Packaging (SLIP) with embedded passive components and optimized
 on-chip and off-chip communications in a seamless integration manner
• Knowledge on RF and HF properties of WLP and SLIP and their mixed-signal
 applications for short-distance communication devices such as Bluetooth and WLAN
• Knowledge of chip/package/system co-simulation and signal integrity issues, design
 guidelines for high performance and noise rejection techniques for such compact
• Competence and activities in state-of-the-art package research societies nationally and
• Courses in EPROPER graduate school for Students both from universities and
 industries (Mixed-Signal System Design, Electronic System Packaging, Physical
 Architecture Design for VLSI Systems, Digital System Engineering)
• Breeding new generation system/electronic engineers for Swedish industry with
 competence knowledge in system/package/chip and mixed-signal issues

1. From chip/system perspective, seamless electronic integration is highly desirable

2. Our competence and activities in EPROPER were reviewed:
        SLIP: material, process, characterization
        Signal transmission & signal integrity: modeling and measurement
        Power distribution systems: chip/package/system unified & efficient modeling
        Competence in chip/package/system: design, modeling, measurement, silicon technology

3. Our planned research will focus on
       Seamless modeling and simulation for system integration;
       Chip/package/system co-design;
       Processing work: experimental verification & extension of silicon technology

       Three new Ph.D. projects

4. Education: breed new generation electronic/system engineers with competence knowledge


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