Phone: (201) 532 1820 HARSH MURARKA 470, 16th Street NW, Apt 5028. email@example.com http://www.cc.gatech.edu/~hmurarka Atlanta GA-30363 EDUCATION • Master of Science in Computer Science, Georgia Institute of Technology, Atlanta, Georgia [GPA 3.87] Expected Dec '10 • Bachelor of Engineering in Computer Science, R.V. College Of Engg., Bangalore, India [GPA 3.50] Sept '03 - Jun '07 PROFESSIONAL EXPERIENCE • High Performance Arch Lab, Georgia Tech., Atlanta, Graduate Research Assistant Aug '10 – Present • Advisor: Prof. Hyesoon Kim Jan '10 – May '10 - Worked on MacSim, a Trace driven simulator, designed to simulate many core heterogeneous architecture. - Developed and integrated various components including cache, re-order buffer, allocation, scheduling, etc. - Verified and Validated MacSim's results with NVIDIA GPU(Tesla architecture) for various benchmarks involving compute intensive instructions, coalesced & un-coalesced access of memory, matrix multiplication, etc. - Documented MacSim Internals and users guide to be used by the users after its planned release in to the Open Source Community in Dec 2010. • NetApp Inc., Pittsburgh, Pennsylvania, Intern May '10 – Aug '10 - Developed Cluster Session Manager (CSM) DevTest which exposed the kernel module's code base to the testing infrastructure via the command line interface(CLI). • NetApp Inc., Bangalore, India, Sustaining Engineer July '07 - July '09 - Worked as a Kernel debugger for NetApp's Operating System “Data ONTAP”. - Was promoted in the team to a Subject Matter Expert (SME) for Memory & Stack issues. - Worked on WAFL (file-system), RAID, storage, protocols like CIFS & NFS and Snap-shot based products. - Awarded “Outstanding Contribution to project RCA for software ONTAP Bugs”, October,'08. • SoftJin Technologies, Bangalore, India, Intern Jan '07 - May '07 - Designed and implemented a library to create Binary Decision Diagram. - Implemented graph-based algorithms for Boolean Function Manipulation. PROJECTS • Simulator for measuring performance (Guided by: Prof. Hyesoon Kim) Aug '09 – Dec '09 - Designed and implemented a simultaneous multi-threading simulator for a super-scalar processor. [C] - Integrated a G-share branch predictor and data cache architecture with multiple tag-store. - Implemented register renaming based on Tomasulo's Algorithm to allow optional Out-of-order execution. - Created performance indicator for factors including Instructions per cycle, branch prediction accuracy and memory hits for a given trace. • Credit Scheduler for Thread Library Feb '10 - Mar '10 - Designed a schedular which takes into consideration user defined credit allocation, fairness, [C] work-conservation, Voluntary and involuntary Pre-emption while scheduling threads on the processor. • Preventing Greed Aug '09 – Dec '09 - Designed a scheme to prevent malicious elements in a peer to peer n/w from exploiting Pastiche's backup model [Java] - Implemented the scheme over Free-Pastry to demonstrate its efficacy in preventing greed in the network. • Addressing Reliability in a Volunteer Computing Setup Aug, 09 – Dec, 09 - Designed and implemented a model for real time job execution over peer to peer setups. [Java] - Implemented a Map-reduce framework over the designed setup for real time jobs. LANGUAGE SKILLS & TECHNOLOGIES • Operating Systems: Linux, Windows. • Programming Languages: C, C++, Assembly, Perl, C#, Java. • Tools: GNU Debugger (gdb), Cscope, Eclipse, Perforce. COURSES - High Performance Computer Architecture, Advanced Operating System, Distributed Computing, Real Time Systems, Dynamic Compilation & Managed Runtime, Programming Language and Computability & Algorithms.