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Serial ATA Technical Change Request and Submission

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					                                    Serial ATA Revision 2.5 Technical Errata


                                                  Change ID                 006

                                                  Applicable Spec.          Serial ATA 2.5




Submission info

Name                               Company                           Date
Brian Dees                         Intel                             2/21/2006


Description of the specification technical flaw

The wrong state number for the link receive state L_RcvData is used in the text describing the
transitions.

Section 10.3.10 includes an incorrect spelling of “Command” within the LBA Mid definition.

A clarification to sections 10.3.10.3 and 10.3.10.5 must be made to ensure that the host needs
to update all shadow registers upon reception of a PIO Setup FIS.


This erratum addresses the corrections listed above.
Description of the correction:


 Modify the transition LR1:2 in section 9.6.4 as shown:

 Transition LR1:2: When the Link layer receives an SOFP primitive from the Phy layer, the Link
 layer shall make a transition to the LR2 LR3: L_RcvData state.


 Modify section 10.3.10 as shown:

 10.3.10             PIO Setup – Device to Host


      0               Error                       Status      R I D R        PM Port         FIS Type (5Fh)

                      Device                    LBA High              LBA Mid                    LBA Low
      1

                 Reserved (0)              LBA High (exp)          LBA Mid (exp)           LBA Low (exp) (0)
      2

                     E_Status                  Reserved (0)      Sector Count (exp)           Sector Count
      3

                                Reserved (0)                                    Transfer Count
      4


                                 Figure 1 – PIO Setup - Device to Host FIS layout

 Field Definitions

            FIS Type - Set to a value of 5Fh. Defines the rest of the FIS fields. Defines the length of the FIS
                  as five Dwords.
            LBA Mid - Holds the contents of the LBA Mid register of the Commandf Block.
            LBA Mid (exp) – Contains the contents of the expanded address field of the Shadow Register
                  Block
            LBA High - Holds the contents of the LBA High register of the Command Block.
            LBA High (exp) – Contains the contents of the expanded address field of the Shadow Register
                  Block
            D - Indicates the data transfer direction. When set to one the transfer is from device to host,
                  when cleared to zero the transfer is from host to device.
            Device - Holds the contents of the Device register of the Command Block.
            Status - Contains the new value of the Status register of the Command Block for initiation of
                  host data transfer.
            Error - Contains the new value of the Error register of the Command Block at the conclusion of
                  all subsequent Data to Device frames.
            I - Interrupt bit. This bit reflects the interrupt bit line of the device. Devices shall not modify the
                  behavior of this bit based on the state of the nIEN bit received in Register – Host to Device
                  FISes.
            PM Port – When an endpoint device is attached via a Port Multiplier, specifies the device port
                  address that the FIS is received from. This field is set by the Port Multiplier. Endpoint
                  devices shall set this field to 0h.
            R – Reserved – shall be cleared to zero.
            Sector Count - Holds the contents of the sector count register of the Command Block.
            Sector Count (exp) – Contains the contents of the expanded address field of the Shadow
                Register Block
            LBA Low - Holds the contents of the LBA Low register of the Command Block.
            LBA Low (exp) – Contains the contents of the expanded address field of the Shadow Register
                Block
            E_Status - Contains the new value of the Status register of the Command Block at the
                conclusion of the subsequent Data FIS.
            Transfer Count – Holds the number of bytes to be transferred in the subsequent Data FIS. The
                Transfer Count value shall be nonzero and the low order bit shall be zero (even number of
                bytes transferred).


 Modify section 10.3.10.3 as shown:

 10.3.10.3 Reception of PIO Setup by Host Prior to a Data Transfer from Host to Device
 Upon receiving a PIO Setup – Device to Host FIS, the host shall update all transfer the Status and Error
 values into the Status and Error Shadow registers and shall hold the E_Status value in a temporary
 register. The Transfer Length value shall be loaded into a countdown register. Upon detecting the change
 in the Status shadow register, host software proceeds to perform a series of write operations to the Data
 shadow register, which the host adapter shall collect to produce a Data FIS to the device. Each write of
 the Data shadow register results in another word of data being concatenated into the Data FIS, and the
 countdown register being decremented accordingly. The E_Status value shall be transferred to the Status
 shadow register within 400 ns of the countdown register reaching terminal count. In the case that the
 transfer length represents an odd number of words, the last word shall be placed in the low order (word 0)
 of the final Dword and the high order word (word 1) of the final Dword shall be padded with zeros before
 transmission. This process is repeated for each and every data FIS needed to complete the overall data
 transfer of a command.


 Modify section 10.3.10.5 as shown:

 10.3.10.5 Reception of PIO Setup by Host Prior to a Data Transfer from Device to Host
 Upon receiving a PIO Setup – Device to Host FIS for a device to host transfer, the host shall hold the
 Status, Error, and E_Status values in temporary registers. The Transfer Length value shall be loaded into
 a countdown register. Upon reception of a Data FIS from the device, the host shall update all Status and
 Error values are loaded into the Status and Error Shadow registers and host software proceeds to perform
 a series of read operations from the Data shadow register. Each read of the Data shadow register results
 in a countdown register being decremented accordingly. The E_Status value shall be transferred to the
 Status shadow register within 400 ns of the countdown register reaching terminal count. This process is
 repeated for each and every data FIS needed to complete the overall data transfer of a command.




Disposition log
2/21/2006         Initial release
3/13/2006         Additional clarifications and corrections included within this errata for review.




Technical input submitted to the Serial ATA International Organization is subject to the terms of
the SATA-IO contributor’s agreement.

				
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