RTL Verilog

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					          241-441
Digital Design And Synthesis
               Lecture 3

      Structural Verilog Continued
     Timing Controls for Simulation
              Testbenches
      Advanced Structural Verilog
       Introduction to RTL Verilog
Module Port List
   Two basic ways to declare the ports of a module

      module xor_8bit(out, a, b);
        output [7:0] out;
        input [7:0] a, b;
        …
      endmodule


      module xor_8bit(output [7:0] out, input [7:0] a, b);
                     …
      endmodule

   Note that each port after a vector declaration
    will be a vector; need to use , input port_x, to
    have scalar ports again.
                                                             2
Example: Hierarchical Multiplexer
   8-to-1 Multiplexer
module mux_8_to_1(
      output out,
      input in0, in1, in2, in3, in4, in5, in6, in7,
      input [2:0] select
);

   Built up from 2-to-1 multiplexers
                  module mux_2_to_1(output out,
                                     input in0, in1,
                                     input select);
                    wire n0, n1, n2;


                  endmodule                            3
Timing Controls For Simulation
   Can put “delays” in a Verilog design
     Gates, wires, even behavioral statements!
   SIMULATION
     Used to approximate “real” operation while simulating
     Used to control testbench
   SYNTHESIS
     Synthesis tool IGNORES these timing controls
          Cannot tell a gate to wait 1.5 nanoseconds!
          Delay is a result of physical properties!
       The only timing that can be (easily) controlled is on a
        clock-cycle basis
          Can tell synthesizer to attempt to meet cycle-time restriction
                                                                            4
Zero Delay vs. Unit Delay
   When no timing controls specified: zero delay
     Unrealistic – even electrons take time to move
     OUT is updated same time A and/or B change:
              and(OUT, A, B)
   Unit delay often used
     Not accurate either, but closer…
     “Depth” of circuit does affect speed!
     Easier to see how changes propagate through circuit
     OUT is updated 1 “unit” after A and/or B change:
              and #1 A0(OUT, A, B);

                                                            5
 Zero/Unit Delay Example
 A          Z
      Y                 Zero Delay                 Unit Delay
 B                                             T   A B C    Y   Z
 C                  T   A B C        Y   Z     0   0 1 0    x   x
                   0    0 0 0        0    0    1   0 1 0    0   x
                   1    0 0 1        0    0    2   0 1 0    0   0
Zero Delay:        2    0 1 0        0    0    3   0 1 1    0   0
Y and Z change     3    0 1 1        1    1    4   0 1 1    1   0
at same “time”     4    1 0 0        0    1    5   0 1 1    1   1
as A, B, and C!    5    1 0 1        0    1    6   1 0 0    1   1
                   6    1 1 0        0    1    7   1 0 0    0   1
                   7    1 1 1        1    1    8   1 1 1    0   1
Unit Delay:        8    0 0 0        0    0    9   1 1 1    1   1
Y changes 1 unit   9    0 0 1        0    0   10   1 0 0    1   1
after B, C         10   0 1 0        0    0   11   1 0 0    0   1
                   11   0 1 1        1    1   12   0 1 0    0   1
                   12   1 0 0        0    1   13   0 1 0    0   0
Unit Delay:        13   1 0 1        0    1   14   0 1 1    0   0
Z changes 1 unit   14   1 1 0        0    1   15   0 1 1    1   0
after A, Y         15   1 1 1        0    1   16   0 1 1    1   1
                                                                    6
Types Of Delays
   Inertial Delay (Gates)
     Suppresses pulses shorter than delay amount
     In reality, gates need to have inputs held a certain
        time before output is accurate
       This models that behavior
   Transport Delay (Nets)
     “Time of flight” from source to sink
     Short pulses transmitted
   Not critical for most of class
     May need to know when debugging
     Good to know for building very accurate simulation
                                                             7
Delay Examples
   wire #5 net_1;                // 5 unit transport delay

   and #4 (z_out, x_in, y_in);   // 4 unit inertial delay
   assign #3 z_out = a & b;      // 3 unit inertial delay

 wire #2 z_out;                  // 2 unit transport delay
 and #3 (z_out, x_in, y_in);     // 3 for gate, 2 for wire

 wire #3 c;                      // 3 unit transport delay
 assign #5 c = a & b;            // 5 for assign, 3 for wire

                                                                8
Delays In Testbenches
   Most common use in class

   A single testbench will test many possibilities
     Want to examine each case separately
     Spread them out over “time”

   Use to generate a clock signal
     Example later in lecture


                                                      9
Analog Simulation
   Divide “time” into slices
   Update information in whole circuit at each slice
   Used by SPICE

   Allows detailed modeling of current and voltage
   Computationally intensive and slow

   Don‟t need this level of detail for most digital
    logic simulation

                                                        10
Digital Simulation
   Could update every signal on input change
    0              1          0               1
    0        1         1      0         0             1
                  1                0         1
    1    1                    0
    1        1                1         1
    0                         0


   Could update just the full path on input change
    0              1          0               1
    0        1          1     0         0             1
                  1                0         1
    1    1                    0
    1        1                1         1
    0                         0


   Don‟t even need to do that much work!
                                                      11
Event-Driven Simulation
   When an input to the simulating circuit changes,
    put it on a “changed” list
   Loop while the “changed” list isn‟t empty:
     Remove a signal from the “changed” list
     For each sink of the signal
        Recompute its new output(s)
        For any output(s) that have changed value, add that signal
         to the “changed” list
   When the “changed” list is empty, keep
    simulation results until next input change

                                                                      12
Simulation
   Update only if changed
    0                   1            0                1
    0             1          1       0           0        1
                       1                   0          1
    1       1                        0
    1             1                  1          1
    0                                0




   Some circuits are very large
         Updating every signal => very slow simulation
         Event-driven simulation is much faster!


                                                          13
Simulation of Verilog
   Need to verify your design
     “Unit Under Test” (UUT)
   Use a “testbench”!
     Special Verilog module with no ports
     Generates or routes inputs to the UUT
     Outputs information about the results

    Inputs         Outputs            Stimulus   Inputs         Outputs
             UUT                OR                        UUT
                   (Response)                                   (Response)

Testbench                            Testbench
                                                                      14
Simulation Example

module adder4b (sum, c_out, a, b, c_in);
  input       [3:0] a, b;
  input              c_in;
  output      [3:0] sum;
  output             c_out;
  assign {c_out, sum} = a + b + c_in;
endmodule

                        4
               a[3:0]                      4
                        4                      sum[3:0]
              b[3:0]        adder4b
                                               c_out
                c_in
                                                          15
Simulation Example
       t_adder4b

                      4
             a[3:0]                 4
                      4   adder4b       sum[3:0]
             b[3:0]        (UUT)        c_out
              c_in




   Testbenches frequently named
       t_<UUT name>
                                                   16
  Example
                                not an
                                apostrophe!

 `timescale 1ns /1ns                            // time_unit/time_precision
 module t_adder4b;
    reg[8:0] stim;                              // inputs to UUT are regs
    wire[3:0] S;                                // outputs of UUT are wires
    wire C4;
                                                             all inputs grouped
UUT                                                          into single vector
      // instantiate UUT
      adder4b(S, C4, stim[8:5], stim[4:1], stim[0]);         (not required)

     // stimulus generation
     initial begin
            stim = 9'b000000000;                //   at   0 ns
            #10 stim = 9'b111100001;            //   at   10 ns     see “response”
Behav. #10 stim = 9'b000011111;                 //   at   20 ns     to each of these
Verilog: #10 stim = 9'b111100010;               //   at   30 ns     input vectors
“do this #10 stim = 9'b000111110;               //   at   40 ns
once”       #10 $stop;                          //   at   50 ns – stops simulation
     end                  timing control
 endmodule                for simulation
                                                                                       18
Testbench Requirements
   Instantiate the unit being tested (UUT)
   Provide input to that unit
     Usually a number of different input combinations!
   Watch the “results” (outputs of UUT)
     Can watch ModelSim Wave window…
     Can print out information to the screen or to a file




                                                             19
Output Test Info
   A number of system calls to output info
     $monitor
          Output the given values whenever one changes
          Can use when simulating Structural, RTL, and/or Behavioral
       $display, $strobe
          Output specific information as if printf or cout in a program
          Used in Behavioral Verilog
   Can use formatting strings with these commands
   Also systems calls that write to files
   Only means anything in simulation
     Ignored by synthesizer
                                                                           20
Output Format Strings
   Formatting string
     %h, %H            hex
     %d, %D            decimal
     %o, %O            octal
     %b, %B            binary
     %t                time
   $monitor(“%t: %b %h %h %h %b\n”,
                  $time, c_out, sum, a, b, c_in);

   Can get more details from Verilog standard
                                                    21
Output Example
`timescale 1ns /1ns                         // time_unit/time_precision
module t_adder4b;
   reg[8:0] stim;                           // inputs to UUT are regs
   wire[3:0] S;                             // outputs of UUT are wires
   wire C4;
                                                      All values will run
  // instantiate UUT                                  together, easier to read
  adder4b(S, C4, stim[8:5], stim[4:1], stim[0]);      with formatting string
  // monitor statement
  initial $monitor($time, C4, S, stim[8:5], stim[4:1], stim[0]);
  // stimulus generation
  initial begin
         stim = 9'b000000000;               // at 0 ns
         #10 stim = 9'b111100001;           // at 10 ns
         #10 stim = 9'b000011111;           // at 20 ns
         #10 stim = 9'b111100010;           // at 30 ns
         #10 stim = 9'b000111110;           // at 40 ns
         #10 $stop;                         // at 50 ns – stops simulation
  end
endmodule
                                                                             22
Exhaustive Testing
   For combinational designs w/ up to 8 or 9 inputs
     Test ALL combinations of inputs to verify output
     Could enumerate all test vectors, but don‟t…
     Generate them using a “for” loop!
       reg [4:0] x;
       initial begin
                for (x = 0; x < 16; x = x + 1)
                       #5     // need a delay here!
       end
   Need to use “reg” type for loop variable? Why?

                                                         23
Why Loop Vector Has Extra Bit
   Want to test all vectors 0000 to 1111
        reg [3:0] x;
        initial begin
                for (x = 0; x < 16; x = x + 1)
                       #5 // need a delay here!
        end
   If x is 4 bits, it only gets up to 1111 => 15
     1100 => 1101 => 1110 => 1111 => 0000 => 0001
   x is never >= 16… so loop goes forever!

                                                    24
Exhaustive Testing Example: UUT

 module Comp_4_str(A_gt_B, A_lt_B, A_eq_B, A, B);
 output       A_gt_B, A_lt_B, A_eq_B;
 input [3:0] A, B;
   // Code to compare A to B
   // and set A_gt_B, A_lt_B, A_eq_B accordingly
 endmodule




                                                    25
Exhaustive Testing Example: Testbench
module t_Comp_4_str();
wire   A_gt_B, A_lt_B, A_eq_B;
reg    [4:0] A, B;                 // sized to prevent loop wrap around
wire   [3:0] A_bus, B_bus;
assign A_bus = A[3:0];             // display only 4 bit values
assign B_bus = B[3:0];

Comp_4_str M1 (A_gt_B, A_lt_B, A_eq_B, A[3:0], B[3:0]);           // UUT

initial $monitor(“%t A: %h B: %h AgtB: %b AltB: %b AeqB: %b”,
    $time, A_bus, B_bus, A_gt_B, A_lt_B, A_eq_B);
initial #2000 $finish;            // end simulation, quit program

initial begin
#5 for (A = 0; A < 16; A = A + 1) begin      // exhaustive test of valid inputs
     for (B = 0; B < 16; B = B + 1) begin #5; // may want to test x‟s and z‟s
     end // first for
    end // second for                             note multiple
end // initial                                    initial blocks
endmodule
                                                                            26
Generating Clocks
   Wrong way:
       initial begin
         #5 clk = 0;
         #5 clk = 1;
         #5 clk = 0;
         … (repeat hundreds of times)
       end
   Right way:
       initial clk = 0;                 initial begin
       always @(clk) clk = #5 ~clk;          clk = 0;
                                             forever #5 clk = ~clk;
                                        end
   LESS TYPING
   Easier to read, harder to make mistake                            27
FSM Testing
   Response to input vector depends on state
   For each state:
     Check all transitions
     For Moore, check output at each state
     For Mealy, check output for each transition
     This includes any transitions back to same state!


   Can be time consuming to traverse FSM
    repeatedly…
                                                          28
Example : Gray Code Counter
   Write a testbench to test a 3-bit gray code
    counter.
       module gray_counter(out, clk, rst);
   In this example, rst is treated as an input to the
    combinational logic (a synchronous reset).
   Initially reset the counter and then test all
    states, but do not test reset in each state.




                                                         29
Solution : Gray Code Counter – Test1
module t1_gray_counter();
  wire [2:0] out;
  reg clk, rst;
  gray_counter GC(out, clk, rst); // UUT

   initial $monitor(“%t out: %b rst: %b ”, $time, out, rst); // no clock
   initial #100 $finish;      // end simulation, quit program

  initial begin
    clk = 0; forever #5 clk = ~clk; // What is the clock period?
  end
  initial begin
    rst = 1; #10 rst = 0;
   end // initial
endmodule




                                                                       30
Simulation: Gray Code Counter – Test1
#       0   out: xxx rst: 1   //   reset system
#       5   out: 000 rst: 1   //   first positive edge
#      10   out: 000 rst: 0   //   release reset
#      15   out: 001 rst: 0   //   traverse states
#      25   out: 011 rst: 0
#      35   out: 010 rst: 0
#      45   out: 110 rst: 0
#      55   out: 111 rst: 0
#      65   out: 101 rst: 0
#      75   out: 100 rst: 0
#      85   out: 000 rst: 0
#      95   out: 001 rst: 0


                                                         31
Force/Release In Testbenches
   Allows you to “override” value FOR SIMULATION
   Does NOT apply to hardware
     Can‟t tell the synthesis tools “when you get here,
        make this value become 3‟d5”
       Synthesizer won‟t allow force…release
   How does this help testing?
     Pinpoint bug by controlling other signals
     Can use with FSMs to override state
          Force to a state
          Test all edges/outputs for that state
          Force the next state to be tested, and repeat
   Can also use simulator force functionality
                                                           32
Force/Release Example

assign y = a & b;
assign z = y | c;
initial begin               t    a   b   c   y   z
  a = 0; b = 0; c = 0;      0    0   0   0   0   0
  #5 a = 0; b = 1; c = 0;   5    0   1   0   0   0
  #5 force y = 1;           10   0   1   0   1   1
  #5 b = 0;                 15   0   0   0   1   1
  #5 release y;             20   0   0   0   0   0
  #5 $stop;
end


                                                     33
Example : Gray Code Counter – Test2
   Write a testbench to exhaustively test a 3-bit
    gray code counter.
       module gray_counter(out, clk, rst);
   Initially reset the counter and then test all
    states, then test reset in each state.
   Remember that in this example, rst is a
    synchronous reset.




                                                     34
Example : Gray Code Counter – Test2
module t2_gray_counter();
  wire [2:0] out;
  reg clk, rst;
  gray_counter GC(out, clk, rst); // UUT

   initial $monitor(“%t out: %b rst: %b ”, $time, out, rst); // no clock
   initial #300 $finish;      // end simulation, quit program

   initial begin
     clk = 0; forever #5 clk = ~clk; // What is the clock period?
   end
   initial begin
     rst = 1; #10 rst = 0;
     #90 rst = 1; force GC.ns = 3'b001; #10 release GC.ns;
     #10 force GC.ns = 3'b011; #10 release GC.ns;
     #10 force GC.ns = 3'b010; #10 release GC.ns;

    …
   end // initial
endmodule
                                                                       35
Simulation: Gray Code Counter – Test2
#   0 out: xxx rst: 1    # 100 out: 001 rst: 1   #   215   out:   000   rst:   1
#   5 out: 000 rst: 1    # 105 out: 000 rst: 1   #   225   out:   101   rst:   1
#   10 out: 000 rst: 0   // at #115 out = 000    #   235   out:   000   rst:   1
#   15 out: 001 rst: 0   # 125 out: 001 rst: 1   #   245   out:   100   rst:   1
#   25 out: 011 rst: 0   # 135 out: 000 rst: 1   #   255   out:   000   rst:   1
#   35 out: 010 rst: 0   # 145 out: 011 rst: 1
#   45 out: 110 rst: 0   # 155 out: 000 rst: 1
#   55 out: 111 rst: 0   # 165 out: 010 rst: 1
#   65 out: 101 rst: 0   # 175 out: 000 rst: 1
#   75 out: 100 rst: 0   # 185 out: 110 rst: 1
#   85 out: 000 rst: 0   # 195 out: 000 rst: 1
#   95 out: 001 rst: 0   # 205 out: 111 rst: 1

                                                                               36
Concatenating Vectors
   Can “build” vectors using smaller vectors and/or
    scalar values                       becomes
   Use the {} operator                 8-bit vector:
                                        a1a0b1b0c1c0da2
   Example
        module concatenate(out, a, b, c, d);
          input [2:0] a;
          input [1:0] b, c;
          input d;
          output [9:0] out;

           assign out = {a[1:0],b,c,d,a[2]};

        endmodule

                                                      37
Concatenating Vectors
   Can “build” vectors using smaller vectors and/or
    scalar values                       becomes
   Use the {} operator                 8-bit vector:
                                        b4b3b2b1b0c1c0d
   Example
        module add_concatenate(out, a, b, c, d);
          input [7:0] a;
          input [4:0] b;
          input [1:0] c;
          input d;
          output [7:0] out;

           add8bit A8(.sum(out), .cout(), .a(a), .b({b,c,d}), .cin());

        endmodule
                                                                    38
Arrays Of Instances
   Need several instances with similar connections?
   Can create an array of instances!
   Works for both primitives and modules

   Syntax:
    <type> [<delay>] <array name> [<range>] (<ports>);

   Example:
       wire [7:0] a, b, out;
       and #4 AND8 [7:0] (out, a, b);

                                                     39
Simple Array Example [1]
   Make an array of instances with each instance
    having same connections


       module array_of_xor (y, a, b);
          input [3:0] a,b;
          output [3:0] y;
          xor X3 (y[3], a[3], b[3]); // instantiates 4 xor gates
          xor X2 (y[2], a[2], b[2]);
          xor X1 (y[1], a[1], b[1]);
          xor X0 (y[0], a[0], b[0]);
       endmodule




                                                                   40
Simple Array Example [1]
   Make an array of instances with each instance
    having same connections


       module array_of_xor (y, a, b);
         input [3:0] a,b;
         output [3:0] y;




       endmodule


                                                    41
Simple Array Example [2]
   Make an array of instances with each instance
    having same connections
      module array_of_flops (q, data_in, clk, set, rst);
         input [7:0] data_in;           // one per flip-flop
         input clk, set, rst;           // shared signals
         output [7:0] q;                // one per flip-flop
         /* instantiate 8 flip-flops to form an 8-bit register */
         flip_flop R7(q[7], data_in[7], clk, set, rst);
         flip_flop R6(q[6], data_in[6], clk, set, rst);
         flip_flop R5(q[5], data_in[5], clk, set, rst);
         flip_flop R4(q[4], data_in[4], clk, set, rst);
         flip_flop R3(q[3], data_in[3], clk, set, rst);
         flip_flop R2(q[2], data_in[2], clk, set, rst);
         flip_flop R1(q[1], data_in[1], clk, set, rst);
         flip_flop R0(q[0], data_in[0], clk, set, rst);
      endmodule
                                                                    42
Simple Array Example [2]
   Make an array of instances with each instance
    having same connections
      module array_of_flops (q, data_in, clk, set, rst);
        input [7:0] data_in;           // one per flip-flop
        input clk, set, rst;           // shared signals
        output [7:0] q;                // one per flip-flop
        /* instantiate 8 flip-flops to form an 8-bit register */




      endmodule



                                                                   43
Example: 8-bit Multiplexer
Use the module:
  mux_4_to_1(ouput out, input in0, in1, in2, in3, input [1:0] sel);

module mux_4_to_1_8bit(output [7:0] out,
                       input [7:0] in0, in1, in2, in3,
                       input [1:0] sel);




endmodule




                                                                      44
Example: 4-Entry Register File
module regfile_4(output [15:0] out, input [1:0] addr,
                                    input [15:0] data, input wr, clk, rst);

The design should use the following modules:

  // 2-to-4 line decoder with enable
  decoder_2_to_4(output [3:0] D, input [1:0] A, input en);

  // 16-bit register with enable, clock, and reset
  register_16bit(output [15:0] q, input [15:0] d, input en, clk, rst);

  // 16-bit 4-to-1 multiplexer
  mux_4_to_1_16bit(output [7:0] out, input [7:0] in0, in1, in2, in3,
                                         input [1:0] sel);




                                                                      45
Interface: 4-Entry Register File
module regfile_4(output [15:0] out, input [1:0] addr,
                 input [15:0] data, input wr, clk, rst);

  wire [3:0] wr_en;
  wire [15:0] reg0, reg1, reg2, reg3;




endmodule

                                                           46
Complex Array Example
   Use an array to build a multi-bit adder
     Caution: carry chain!
      module 4_bit_adder(sum, c_out, a, b, c_in);
        input [3:0] a, b;
        input c_in;                      the carry signals
        output [3:0] sum;                don’t line up the way
        output c_out;                    the other signals do!
        wire [3:1] c;

        Add_full M3(sum[3], c_out, a[3], b[3], c[3]);
        Add_full M2(sum[2], c[3], a[2], b[2], c[2]);
        Add_full M1(sum[1], c[2], a[1], b[1], c[1]);
        Add_full M0(sum[0], c[1], a[0], b[0], c_in);
      endmodule
                                                                 47
Complex Array Example
   Use an array to build a multi-bit adder
     Caution: carry chain!
      module 4_bit_adder(sum, c_out, a, b, c_in);
        input [3:0] a, b;
        input c_in;           use concatenation to form vectors!
        output [3:0] sum;
        output c_out;
        wire [3:1] c;

        Add_full M[3:0](sum, {c_out, c[3:1]}, a, b, {c[3:1], c_in});
      endmodule




                                                                   48
RTL Verilog
   Higher-level of description than structural
     Don‟t always need to specify each individual gate
     Can take advantage of operators

   More hardware-explicit than behavioral
     Doesn‟t look as much like software
     Frequently easier to understand what‟s happening

   Very easy to synthesize
     Supported by even primitive synthesizers

                                                          49
Continuous Assignment
   Implies structural hardware
       assign <LHS> = <RHS expression>;

   Example
       wire out, a, b;
       assign out = a & b;

   If RHS result changes, LHS is updated with new value
      Constantly operating (“continuous”!)
      It‟s hardware!

   Used to model combinational logic and latches
                                                           50
Full Adder: RTL/Dataflow
   Note use of operators                  A
                                                        S
                                           B
                                          CI
      module fa_rtl (A, B, CI, S, CO) ;

      input A, B, CI ;                                  CO
      output S, CO ;

      // use continuous assignments            fa_rtl
      assign S = A ^ B ^ CI;
      assign C0 = (A & B) | (A & CI) | (B & CI);

      endmodule


                                                        51
Continuous Assignment LHS
   Can assign values to:
     Scalar nets
     Vector nets
     Single bits of vector nets
     Part-selects of vector nets
     Concatenation of any of the above
   Examples:
       assign out[7:4] = a[3:0] | b[7:4];
       assign val[3] = c & d;
       assign {a, b} = stimulus[15:0];

                                            52
Continuous Assignment RHS
   Use operators:
     Arithmetic, Logical, Relational, Equality, Bitwise,
        Reduction, Shift, Concatenation, Replication,
        Conditional
       Same set as used in Behavioral Verilog
   Can also be a pass-through!
       assign a = stimulus[16:9];
       assign b = stimulus[8:1];
       assign cin = stimulus[0];
     Note: “aliasing” is only in one direction
          Cannot give „a‟ a new value elsewhere to set stimulus[16:9]!
                                                                      53
Example: adder4b

module adder4b (sum, c_out, a, b, c_in);
  input       [3:0] a, b;
  input              c_in;
  output      [3:0] sum;
  output             c_out;
  assign {c_out, sum} = a + b + c_in;
endmodule

                        4
               a[3:0]                      4
                        4                      sum[3:0]
              b[3:0]        adder4b
                                               c_out
                c_in
                                                          54
Can Often Replace Primitive Arrays
   Module/Instance Array:
       module array_of_xor (output [3:0] y, input [3:0] a, b);
          xor Xarray [3:0] (y, a, b);    // instantiates 4 xor gates
       endmodule

   Continuous Assign
       module xor_4bit (output [3:0] y, input [3:0] a, b);
          assign y = a ^ b;              // instantiates 4 xor gates
       endmodule

   Can‟t replace array of FF‟s!
     No edge-triggering in continuous assignments!

                                                                       55
Operators: Arithmetic
   Much easier than structural!
        *    multiply         ** exponent
        /    divide           %     modulus
        +    add              -     subtract
   Some of these don‟t synthesize
   Also have unary operators +/- (pos/neg)
   Understand bitsize!
     Can affect sign of result
     Is affected by bitwidth of BOTH sides
              SUM[6:0] = a[3:0] + b[4:0]

                                               56
Example: Unsigned MAC Unit
Design a multiply-accumulate (MAC) unit that computes
    Z[7:0] = A[3:0]*B[3:0] + C[7:0]
It sets overflow to one, if the result cannot be represented using 8 bits.

module mac(output Z [7:0], output overflow,
          input [3:0] A, B, input [7:0] C);




                                                                      57
Solution: Unsigned MAC Unit
module mac(output Z [7:0], output overflow,
             input [3:0] A, B, input [7:0] C);
  wire [8:0] P;
  assign P = A*B + C;
  assign output = P[7:0];
  assign overflow = P[8];
endmodule

Alternative method:

module mac(output Z [7:0], output overflow,
             input [3:0] A, B, input [7:0] C);
  assign {overflow, output} = A*B + C;
endmodule




                                                 58
Operators
   Shift (<<, >>)
   Relational (<, >, <=, >=)
   Equality (==, !=, ===, !==)
     ===, !== test x‟s, z‟s!   ONLY USE FOR SIMULATION!
   Logical Operators (&&, ||, !)
     Build clause for if statement or conditional expression
     Returns single bit values
   Bitwise Operators (&, |, ^, ~)
     Applies bit-by-bit!
   Watch ~ vs !, | vs. ||, and & vs. &&
                                                            59
Example: Comparator
Complete the following module using three continuous assignment
statements.

module compare_4bit(output A_lt_B, A_gt_B, A_eq_B,
                          input [3:0] A, B);




endmodule




                                                                  60
Operators
   Reduction (&, |, ^)
     Unary!
      &(4‟b0111), |(3‟b010), ^(12‟h502)
   Parentheses ( () )
     Use to make calculations clear!
   Concatenation ( {} )
     Assembles vectors
   Replication ( {{}} )
       // a is a 4-bit vector with the value of b
       // as the value of each bit
       wire [3:0] a = {4{b}};

                                                    61
Operators: Conditional
   Can do an “if else” assignment!
        <clause> ? <T exp> : <F exp>
   Examples:
        assign mux_out = sel ? in1 : in0;
        assign and2 = a ? b : 0;
        assign xor2 = in1 ? ~in2 : in2;
        assign triVal = sel ? in : 1‟bz;
   Can nest the conditionals!
        assign trimux = trisel ? (muxsel ? a : b) : 1‟bz;

 Frequently used for tristate, muxing
 Also used for complex combinational logic
 USE PARENTHESES WHEN NESTING!!!
                                                            62
Review Questions
   What are the two ways to declare module ports?
   Why do we perform hierarchical design?
   What is the difference between transport and
    inertial delay? When is each used?
   What does it mean to exhaustively test a
    design?
   Why are force/release statements useful?
   How do you generate a clock with a period of 10
    time units?

                                                  63
Review Questions
   Show how to use array instantiation to create an array of
    6 parallel AND gates, called AND_array, that has a delay
    of 4 time units and takes as inputs X[5:0] and Y[7:2]
    and outputs Z[1:6].
   Repeat the above problem using a single continuous
    assignment statement
   Instantiate a 16-bit 2-to-1 mux using array instantiation
    of the following module:
     mux_2_to_1(ouput out, input in0, in1, sel);
   What do each of the following evaluate to?
        4‟b1000 * 4‟b0100          4‟b1101 & 4‟b1001
        (^ 4‟b1011) + 4‟b0011      4‟b1101 && 4‟b1001

                                                           64

				
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Description: RTL Design, Verilog code, verilog rtl, System Verilog, Verilog language, verilog hdl, Verilog Simulation, coding style, Predicate Abstraction, FPGA design, Abstraction refinement, Design Engineer, Verilog design, synthesis tools, source code,