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					                        An Analog Mixed-Signal Verification Kit for
                          Verification of Analog-Digital Circuits
                          G. Bonfini, M. Chiavacci, R. Mariani, E. Pescari

         YOGITECH SpA, via Lenin 132/p, 56017 San Martino Ulmiano (Pisa), Italia




     The greatest obstacle to a System-on-Chip [SoC] design team’s success is verification. Combining the
complexity of digital verification with the increasing integration of larger and more sophisticated analog
circuits, the problem is getting exponentially worse. This trend not only presents a challenge to the
verification engineers, but to the industry as a whole.
If verification of digital sub-systems is based on advanced techniques such as constraints capture,
randomized or pseudo-randomized stimulus-generation and result collection with functional coverage
evaluation, on the other side the use of hand-coded analog blocks models, manually-verified within a digital
verification environment has been sufficient to provide confidence in a mixed-signal design to sign-off prior to
submitting it for fabrication. However, due to greater levels of integration, changes in process technology and
increasing market pressures and risks, an automated and metric-driven methodology is now required.
    YOGITECH’s proposed approach combines digital and analog circuit verification, providing engineers
with a methodology and a set of intellectual properties to interface verification tools with mixed signal
simulators. This approach allows extending to analog and mixed signal domain concepts and techniques
widely used in state-of-art object-oriented digital functional verification.
    Using a Bandgap cell as case study, the paper shows how the presented solution allows a significant
improvement in verification productivity and quality.




Introduction
     Electronic systems are often mixed signal circuits where huge digital parts work together with
sophisticated analog blocks interfacing the external word (i.e. sensors, actuators etc).
     Due to the complex interaction between analog and digital verification methodologies[2], the overall
verification coverage of a mixed signal system is very often decreased and system bugs appear very late in
the design process. This is often responsible for expensive debugging phase, re-design and silicon re-spins
with an escalation on cost and unpredictability in time to market. Increasing quality in verification of mixed
signal circuit becomes more and more important.
     Mixed signal simulation tools able to link analog and digital blocks simulating them together in the same
test-bench are already available in the market [1] but, normally they are used in an analog oriented
approach. Most of the proposal addressing analog and mixed signal circuit verification are analog oriented
(e.g. from [2] to [7]) and specific for particular applications. This makes really difficult to include complex
digital blocks and to extensively use concepts like stimuli randomization, data and protocol self-checking and
functional coverage; but these are concepts widely recognized to be able to achieve first right silicon.
     In this paper, the innovative verification approach presented, based on some previous works [8][9][10],
consists in a definition and usage of a “verification kit” by which object-oriented functional verification is
extended to mixed signal circuit. Basically the kit includes elements to create analog stimuli, monitor analog
signals and define automatic checks together with a set of ready-to-use verification test-benches for main
analog blocks and functionalities.
     After a description of the verification kit and its features, the verification of a common analog block is
presented as proof-of-concept: the traditional approach used to verify a Bandgap cell is compared to the
proposed one in terms of data collection, coverage analysis and simulation run time. Even if this device is
not considered a complex case study, its verification requires several simulations and significant effort to
collect the results.
The Analog Mixed-Signal verification kit (AMS vKit)
     The Analog Mixed-Signal Verification Kit enables an automated, coverage-driven verification
environment and methodology for top and block-level mixed-signal designs. It comprises an extensible set of
configurable, plug-and-play pre-verified verification components that unify state-of-the-art verification tool, as
Cadence Specman Elite, and mixed-signal simulators to create an Object-Oriented mixed-signal functional
verification environment. It is based on “e” verification language (IEEE P1647 standard [14]), that allows the
verification engineer to capture the rules from specifications and to generate tests automatically.




                                    Figure 1: Block diagram of the AMS vKit


     As illustrated in Figure 1 the analog mixed signal verification kit is composed by three libraries
(vTerminals, vComponents and Sequences data base) and all the necessary infrastructure to make the
full environment working (simulator scripts, “e” structures/unit and classes, etc.)
     The core of the kit is a library of so-called verification terminal (vTerminals) interfacing analog domain
information with digital one. There are two kinds of vTerminals: verification sources (vSources - vS) and
verification probes (vProbes – vP).
     vSources are models of signal sources configured and controlled by digital words coming from verification
domain and providing continuous and time-continuous voltage and current signals or analog events;
examples of vSources are: signal generators, noise injectors, parameters spread emulator, etc.
     vProbes are monitors which transfer analog information coming from mixed-signal simulator to the
verification domain; they provide values of voltage, current and timing parameters and they include self-
checking mechanism (e.g. check if a sampled voltage level is in a pre-defined range); examples of vProbes
are: voltage/current/time detectors, evaluators for linearity, monotonic behavior etc.
     vSources and vProbes are composed by two sections: one implemented in “e” [14] allowing configuration
by the verification tool and one in Analog HDL, such as VerilogAMS [15], implementing signal processing. To
optimize the interaction between simulator and verification tool each vTerminal has a local unit called time-
manager which handles the interface between the two players.
      The verification components (vComponents) are ready-to-use verification environments (e.g. test-
benches) for main blocks, including self-checking mechanism and coverage evaluation based on analog
metrics that are easy to integrate in a complex mixed- signal environment. They are developed to verify main
analog blocks such as band gap cells, oscillators, voltage regulators and so on.
For each cell, the verification plan has been defined including significant parameters, conditions and
procedures to measure them. Based on the verification plan, the verification component drives, monitors and
processes current and voltage signals generating proper stimuli for the DUT and elaborating the information
in order to reach the target functional coverage. The case of the Bandgap cell analyzed in the next sections
explains how one of these vComponents (the one for the Bang gap) is defined and it can be used.
     A verification component includes:
   •   set of vTerminals handling analog data
   •   Bus functional module generating the proper set of stimuli, either directly driving the digital part or
       driving the analog part through the vSources.
   •    Monitor receiving the outputs directly or through the vProbes
   •   Sequence driver handling and synchronizing the whole verification environment.
   •   Scoreboard containing all the data needed to compare the expected responses with the real ones.
   •   Coverage implementing also analog metrics to evaluate the functional coverage of the verification
       process.

    In order to calculate a not trivial analog parameter is necessary to properly control and configure some
vSources and vProbes and to synchronize them. This task is implemented in a clean way using one of the
powerful concepts available in “e”: the sequences [16]. A sequence is a structure that represents a stream of
items signifying a high-level scenario of stimuli. This is done by generating items one after the other,
according to some specific rules.
    The database provided with the kit (sequences DB) includes the sequences needed in an analog
context such as transient power supply sweep, thermal harmonic distortion measurement, etc.
    In addition, configuration files and scripts used to set simulator parameters and define multiple simulation
runs are also included in the Analog Mixed-Signal Verification Kit.



Traditional Approach to verify a Bandgap
   A bandgap cell is a common circuit able to generate a temperature independent output voltage level
equivalent to the band gap level of the silicon [11],[12]. The block considered in the following is depicted in
   Figure 2.


                                       Parameters                  Min           Typ    max         Unit
                                       Power supply (Vdd)          3             3.3    3.6         V
                                       Temperature                 -40           27     150         °C
                                       Output voltage (VOUT)       1,22-1%*      1,22   1,22+ 1%*   V
                                       Settling time               50                   230         µs
                                      * +/- error of 1% is referred to 1.22 V.

                                     Figure 2: Bandgap cell and its specs

    To verify a band gap cell means, in this case, to evaluate its function in each operating conditions
depending on technology process parameters spread, power supply levels and operating temperature.
     Since it has been assumed the availability of a 5-b Trimmer word, the verification item on which focus
the discussion is: “for each process variation exists at least one 5-b Trimmer configuration that guarantees
for the output voltage an absolute maximum error less than 1 % for the whole temperature range”.
    First it is necessary to define the significant operating conditions. For a Bandgap we can assume that the
devices influencing its behavior are BJT and resistors so we can reduce the corner conditions related to
technology parameters spread to only 9 combinations (fast, typical and slow models for BJT combined with
maximum, typical and minimum value for the resistivity). On top we have to consider the power supply
variation and so add 3 conditions for maximum, typical and minimum value (27 different cases in total). In
this case the considered range for the environment temperature is the automotive one (-50°C- 150°C)
sampled in 5 points.
    In the traditional approach, for each condition, we need to simulate each trimmer code and check the
defined item. This can be translated in 27 different simulations with temperature sweep in which the variable
is the trimmer code (from 0 to 31). For example, using Cadence Affirma Analog Artist for one operating
condition, the results are the ones shown in Figure 3.
Figure 3: simulations results for one operating condition (process parameters and voltage supply level) and a
                                    temperature sweep on 32 trimmer codes

    The best response in terms of temperature sensitivity is the curves in the middle but few of them comply
with the specs: in this case the trimmer codes 13, 14 and 15 are in spec (absolute error < 1%). This kind of
simulation has still to be run for 26 times in order to cover all the defined conditions. This procedure does not
allow automatic data collection and the results analysis has to be done from time to time by the designer.
    Some automation exists (i.e. Corner tool) in order to run all the simulations (included process parameter
spread) only once, but in any case results collection and are still expensive in time. Whatever procedure is
used, the simulation run time (Sim_time) can be calculated as follows:

                             Sim_Time =27 * 32 * Sim_Trim                                            (1)

where 27 is the number of the possible process variations (BJT and resistor), 32 is the number of possible
trimmer codes and Sim_trim is the simulation run time of one of the 32 simulations included in a single
parameter simulation. For this case study it is possible to assume 5 s as Sim_trim, thus:

                            Sim_time ≈70 min                                                       (2)

   In addition, it is important to highlight that in (2) the time that the designer spends to collect and analyze
the results is not taken into account and it is considerably high.


Using the AMS vKit
Figure 4 shows the schematic representation of the verification component for the Bandgap cell included in
the AMS vKit. It is possible to recognize a set of vTerminals which drive and collect analog information:
        - vS_vpulse: vSource that generates power supply as voltage pulse;
        - vP_ivalue: vProbe that measures the current consumption;
        - vP_vsettling: vProbe that measures the BandGap settling time at power up;
        - vP_vvalue: vProbe that samples the output voltage value of the DUT
        - IE: interface elements for discipline conversion [15].

                                                       vS_vpulse

                                                       vP_ivalue



                                                      V+
                                                            IB
                                      IE
                                           TR<k-1:0>

                                             Band Gap
                                                                                     vP_settling
                                      IE   PDN              BG

                                                 V-                     C=100fF
                                                                                     vP_vvalue



                                                                   External Components


                                                           BandGap Verification
                                                              Components

                                 Figure 4: Band gap verification environment
    Input stimuli generated by the vSources and the output voltage from the DUT are shown in Figure 5 as
simulation results (from Cadence Simvision waveform viewer).
    The output voltage is sampled by the vP_vvalue (Figure 5): the sampling time is defined by an internal
trigger.




                                     TH_h
                                                    Self checking of
                                                    the output voltage
                                   TH_l
                                                    implemented in
                                                    the vP_vvalue

                                          Trigger

                           Figure 5: Waveforms related to the Bandgap verification

This trigger is configured by the user according to the Bandgap performances (e.g. it must occur after the
maximum settling time at start up to be sure the sampled voltage is stable) and it is part of the time manager
unit of the vP_vvalue.
    It is worth noting that automatic multiple simulations (regression) involving temperature and process
variations are automatically managed by the verification component: the user has to decide the temperature
range (min&max), the temperature step and the model card that need to be investigated. Functional
coverage is evaluated for each simulation and then automatically cumulated for the final result.
    Moreover the verification engine (Cadence Specman Elite) controls the complete simulation and it is able
to change input stimuli strategy depending on collected results: an output result obtained at the time “n” can
produce an effect on a stimulus generated at the time “n+1”. This feature creates a sort of close loop in the
simulation itself and allows implementing smart strategy and saving simulation time. The following procedure
is implemented.
         1. select a set of technology process parameters (named it model card);
         2. select a temperature value
         3. simulate the DUT setting the selected pair of environment conditions (model card, temperature
             value) for each trimmer code and power supply level; if a trimmer code fails (i.e. the bandgap
             output value has an error higher than 1% respect to the specification) at least for one power
             supply level the code is discarded and not used anymore for the other temperature using the
             same model card (close loop capability).
The implemented technique allows a reduction in simulation time avoiding simulating not- significant
conditions. In fact, the trimmer code is used to tune the Bandgap output voltage in a specified range in all the
process corners: different trimmer codes guarantee the performance over the full technology process
spread. So it happens that in one specific condition only few codes give a correct result for the full
temperature range. Based on that, many simulations will give an output voltage out-of-spec by definition and,
in the proposed approach, can be automatically discarded before run.
For the case under study Sim_time = 30 min, less than 50% of the original one.

At the end of the verification process all the results are collected together for the coverage analysis.
Input coverage items:
     - Have all the trimmer codes been used?
     - Have all the model cards been used?
     - Have all the temperature values been used?
     - For each model card, have all the trimmer codes been used?
Output coverage items:
     - For each model card, is there (at least) one trimmer code that guarantees an error less than 1% for
        all temperature values?
    -    For each trimmer code, which are the model cards that guarantee a maximum error less than 1% for
         all temperature values?
   Figure 6 is an example of coverage elaboration and data collection results that compared with the one in
Figure 3 obtained from a traditional approach shows a more compact and clear format. Moreover they do not
need any additional elaboration. The obtained results match the ones related to standard simulation (see
section 2) and results are collected in a comprehensive way, i.e. in detailed reports and they do not rely on
the interpretation of waveforms by the verification engineer as it happens for the traditional approach.

                                        For model card #1, trimmer       trimmer codes 16, 17 are
                                           codes 13, 14, 15 are            functional only for one
                                             functional for all         temperature (power supply
                                        temperature (power supply                  typical)
                                                 typical)




                              Figure 6: functional coverage graphical interface


Conclusion
   The presented approach is valid also for more complex mixed-signal systems: the mixed-signal
verification kit includes an extensible, easy configurable and ready to use set of components which drive,
monitor and process current and voltage signals together with a significant set of coverage items, checks
and test scenarios for most common analog blocks such as DC-DC converters, amplifiers, buffers,
comparators, band gap, voltage reference and power on reset blocks. The user can easily configure the
verification environment through a graphical interface and build different test scenarios. In the same way,
vSources and vProbes can be combined to generate and elaborate any kind of continuous signals.
   The proposed approach offers a highly integrated and automated solution extending the most advanced
techniques for functional dynamic verification to analog circuits. Concepts like pseudo-randomized stimuli,
coverage analysis, scoreboards, and regressions are applied to mixed signal designs drastically reducing
verification time and increasing verification quality.


Reference
        [1] C.Brown, “Mastering of Mixed-Signal Verification” EETIMES, 17 March, 2004
        [2] Bill Luo, Jim Lear, “A Unified Functional Verification Approach for Mixed Analog-Digital ASIC
            Designs”, Legerty INC, DesignCon 2003
        [3] Koji Ara, Kei Suzuki, Hitachi, Ltd, “A Proposal for Transaction-Level Verification with Component
            Wrapper Language”, Proc. of Design Automation and Test in Europe (DATE), March 03-07 2003,
            Munich, Germany
        [4] “IEEE Std VHDL 1076.1-99: The Analog and Mixed Signal Extension for VHDL”, 1999
        [5] B.Li, L.Jia, H.Tenhunen, “Optimization of analog modelling and Simulation”, Proc. of the 5th
            International Conference on Solid-State and Integrated Circuit Technology, 1999, Beijing, China,
            pp.385-388
       [6] A.J. Ginés, E. Peralías, A. Rueda, N. Martínez Madrid and R. Seepold, “A Mixed-Signal Design
            Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects”, Proc. of
            Design Automation and Test in Europe (DATE), March 2002, Paris, France
       [7] E. Peralías, A. J. Acosta, A. Rueda, J. L. Huertas, "A VHDL- based Methodology for the Design
            and Verification of Pipeline A/D Converters", Proc. of Design Automation and Test in Europe
            (DATE), March 2000, Paris, France, pp. 534-538
       [8] R.Mariani, M.Chiavacci, G.Bonfini “Foundamentals of a novel approach for mixed analog-digital
            verification”, 9th IEEE European Test Symposium, Informal Session, Ajaccio (Corsica), 23-26
            May 2004
       [9] G.Bonfini, M.Chiavacci, R.Mariani, R.Saletti “A New Verification Approach for Mixed-Signal
            Systems”, 2005 IEEE International Behavioral Modeling and Simulation Conference(BMAS
            2005),22-23 September 2005, San Jose, California, USA, accepted for web publication;
       [10] G.Bonfini, M.Chiavacci, F.Colucci, F.Gronchi, R.Mariani, E.Pescari, A.Sterpin “Fault Coverage in
            a New Mixed-Signal Verification Environment”, In Proc.of 11th International Mixed-Signal Testing
            Workshop (IMSTW), 27-29 June 2005, Cannes, Franc, pp.148-154
       [11] R.J. Widlar, “New developments in IC voltage regulators”, IEEE J. Solid-State Circuits, vol.SC-6,
            pp.2-7, Feb. 1971
       [12] A.P.Brokaw, “A simple three-terminal IC bandgap reference”, IEEE J. Solid-State Circuits,
            vol.SC-9, pp.388-393, Dec.1974
       [13] Cadence’s Specman tool, www.cadence.com
       [14] IEEE 1647: http://www.ieee1647.org/index.html
       [15] Verilog-AMS Language Reference Manual: “Analog & Mixed-Signal Exstension to Verilog HDL”,
            version 2.1, January 20, 2003
       [16] “e Reuse Methodology (eRM) Developer Manual” Version 2.1, for use with Incisive Enterprise
            Specman Elite 5.0.3 and Incisive Plan-to-Closure Methodology 1.1 Beta chapter 4.



                   Monia Chiavacci
                    She is a co-founder of YOGITECH and she is now responsible for the mixed-signal
                    division. She worked in a VLSI design centre as analog designer from 1998, when she
                    achieved her degree cum laude in Electronic Engineering at the Pisa University, to 2000
                    when she decided for YOGITECH challenge
                    Her work experiences cover a lot of aspects in the field of analog and mixed signal
                    design, high reliability systems in critical environments such as biomedical and space
fields and high voltage automotive application.



                 Riccardo Mariani
                 He holds a Ph.D. in Microelectronics from the University of Pisa and he is co-founder and
                 currently the chief technology officer at YOGITECH. Before founding YOGITECH, he was
                 Technical Director in Aurelia Microelettronica, CAD Laboratory and Team Director in
                 CAEN Microelettronica, Digital Design Responsible and CAD Laboratory Coordinator in
                 Centro TEAM, Digital Design Consultant in Italtel Center of Parma University.
                 Riccardo won SGS-Thomson and Enrico Denoth Best Engineering Award. He is IEEE
member and he has authored many papers related to High-Reliability Circuits, Design for Testability,
Advanced Design Techniques and Asynchronous Circuits.

                       Egidio Pescari
                       He is Senior Digital and Verification Designer of YOGITECH SPA. Graduated at the
                       University of Perugia in 1998, he obtained a grant by INFN of Perugia as a digital
                       designer for safety critical application. Before working in YOGITECH he worked in a
                       VLSI design centre as a digital designer developing system in critical environment
                       such as automotive and space application.
He acquired experience in many automotive protocols such as LIN, CAN... He has experience in the field of
the dynamic verification using the most advanced verification tools and methodologies. He has recently
acquired experience in the verification of mixed signal circuits.
                        Giuseppe Bonfini
                        He is Senior Analog Designer of YOGITECH SPA. He has received his Laurea
                        Degree cum laude in Electronic Engineering from the University of L'Aquila and
                        holds a Ph.D in Microelectronics from the University of Pisa.
                        In 2001 he started to work as analog designer for Aurelia Microelettronica S.p.A.
                        (CAEN group) and Padua University, then he opted for YOGITECH in 2003. He
                        has experience in ultra low-power/low-voltage Analog-to-Digital converter design
                        for biomedical application (cardiac pacemaker), integrated Front-end for ECG
(ElectroCardioGram) acquisition, Voltage Regulator Design for automotive application and Mixed Signal
Verification.

				
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