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					                                        Lab #11:
                    Title: Inverter Capacitances and Switching Time

Objective:
The objective of this lab is to give provide practical experience regarding the parasitic capacitances associated with
discrete logic gates and the dynamic power dissipated.
          1. Measure the propagation time of an inverter under various loads
          2. Determine the input and output capacitance of several discrete inverters
          3. Explore the fan-out of an inverter

Required Datasheets:
       CD4007

Introduction:
Propagation Time
The time required for a CMOS inverter to switch from a low output to a high output is called the low-to-high
propagation time, tpLH. It is defined as the time required for V o to reach 50% of VDD. Similarly, the time required
for a CMOS inverter to switch from a high output to a low output is called the high-to-low propagation time, tpHL.

Input and Output Capacitance
Due to device design and fabrication, CMOS inverters have several parasitic capacitances between device terminals,
as shown in Fig. 1. Each parasitic capacitance will prolong the time required for the input/output voltage to switch.
It would be terribly inconvenient to attempt to determine the time required for voltages to switch by considering
every capacitor individually. A good approximation of the switching times can be obtained by conglomerating the
appropriate capacitances into an input capacitance and an output capacitance, as shown in Fig. 2.

                                         VDD                                                        VDD




                               CGSP            CDSP



               Rs                CGDP
                     Vi                               Vo                     Rs   Vi                        Vo
                                  CGDN
          Vs                                                            Vs
                                               CDSN
                                                                                                           Cout
                                                                                       Cin

                               CGSN




                          Figure 1.                                                     Figure 2.



The output capacitor slows the transition of the output voltage between high and low. The mathematical expression
for Vo is difficult to derive, but it can be shown that the low-to-high propagation time is (1), and the high-to-low
propagation time is given in (2).




South Dakota State University                                            EE321 Electronics II Laboratory Manual
Electrical Engineering Department                                                DarenDavoux        Summer 2008
                                                           1
                    1.65COUT
         t pHL                                                                                (1)
                      
                        W
                   K n  VDD
                       L
                    1.65COUT
         t pLH                                                                                (2)
                       W 
                   K   VDD
                     p
                       L
Before Vo can even begin to switch, Vi must reach the threshold voltage. The input capacitance of the FET creates a
series RC circuit with the source resistance. When VS switches from high to low, Vi will exponentially rise from
0 to VDD according to (3). When t = RsCin, Vi is equal to 0.63VDD. By measuring the time required for Vi to reach
63% of its final value, the input capacitance can be calculated.

                       
                           t
                                    
         Vo  VDD 1  e RS Cin                                                               (3)
                                   
                                   
Fan Out
If multiple inverters were added as loads to an inverter, like shown in Fig. 3, the input capacitance of each load
inverter will further slow the transition of Vo, as though a capacitor were placed in parallel with the output
capacitance of the inverter. This limits the number of load inverters a single CMOS inverter can drive, while
maintaining specified propagation times. This is called fan-out of the inverter.

                                                                                       VDD
                                                         Primary             Load
                                                         Inverter          Inverters

                                                              VDD




                                                                              Cin




                                         Rs   Vi                    Vo
                                                                                       VDD


                                    Vs
                                                                    Cout
                                                   Cin



                                                                              Cin




                                                         Figure 3.


Lab Procedure:
For all experiments, VDD = 5 V

I:       Measure the propagation time of CMOS inverters




South Dakota State University                                                 EE321 Electronics II Laboratory Manual
Electrical Engineering Department                                                     DarenDavoux        Summer 2008
                                                               2
         1.       Using a single CD4007 transistor array, construct three separate CMOS inverters as shown in
                  Fig. 1. Do not include RS (or the capacitors, they account for the parasitic capacitors within the
                  FET).
         2.       Apply a 2 MHz, 0-to-5 V square wave to each inverter. Measure and record images of the
                  input/output voltages of each inverter.
         3.       Measure and record the propagation times for the output to switch from low to high and
                  from high to low. Comment on the matching between inverters and between tpHL and tpLH.
                  Are all the same? How much variance is there between t pLH and tpHL for an individual
                  inverter? Between inverters?

II:      Measure the output capacitance of the inverters:
         Equations (1) and (2) can not be solved for Cout through a single test. First an external capacitance of a
         known size will be added at the load of the inverter, and the values of [K n(W/L)] and [Kp(w/L)] will be
         calculated. Then the external capacitor can be removed and the propagation times measured and Cout
         calculated
         1.       Add an external capacitor of 1 nF to the output of each inverter. Be sure to measure the actual
                  capacitance. Capacitors can vary by as much as 20%.
         2.       Measure and record the propagation times of each inverter, both tpLH and tpHL. The input
                  frequency may need to be reduced substantially. Include images of the input/output voltages.
         3.       Using (1) and (2), assuming Cout is much smaller than 1 nF, calculate the values of [Kn(W/L)]
                  and [Kp(W/L)] for each inverter. Comment on the matching between FETs.
         4.       Using measurements obtained in Part I, with the values of [K n(W/L)] and [Kp(W/L)] calculated
                  above in Step 3, calculate the output capacitance of the inverters. Comment on the size and
                  the matching between inverters.

III:     Measure the input capacitance of each inverter
         By adding a large source resistance and measuring the time required for Vi to transition to 63% of VDD, the
         input capacitance of the inverters can be calculated
         1.       Remove all external capacitors, and add a 100 k resistor as Rs for each inverter like shown in
                  Fig. 1. Measure the actual value used.
         2.       Adjust the frequency of the signal generator until the transition time for Vi can be easily observed
                  and recorded.
         3.       Measure the time required for Vi to increase from 0 V to 0.63VDD, as well as the time
                  required for Vi to fall from VDD to 0.37VDD (which is 63% less than VDD). Record images of
                  the input and output waveforms.
         4.       Using (3) and your measurements, calculate the input capacitance of each inverter. Comment
                  on the matching between devices.

IV:      Explore Fan out of CMOS inverters
         As loads are added to an inverter, the time required for the primary inverter to switch states increases. If
         inverters are the load, the input capacitance of each load inverter adds to the output capacitance of the
         primary inverter.
         1.       Remove Rs and the external capacitors from each inverter, and load one of your inverters with the
                  other two as shown in Fig. 3. Predict the low-to-high and high-to-low propagation time for
                  the primary inverter to switch states, based on measurements and calculations performed in
                  Parts 1 through III.
         2.       Adjust the frequency of Vs until the transition time of the output voltage can be measured.
         3.       Record images of the input voltage and the output voltage of the inverter, and measure the
                  propagation time of the primary inverter. Compare with prediction. Using your calculations
                  of [Kn(W/L)] and [Kp(W/L)] for the primary inverter, calculate the equivalent output
                  capacitance with the two inverters loading the primary. Compare with expectations. Was
                  there deviation?

South Dakota State University                                            EE321 Electronics II Laboratory Manual
Electrical Engineering Department                                                DarenDavoux        Summer 2008
                                                          3
         4.       Calculate the output capacitance required for the propagation times to be 10 times the
                  propagation time of an unloaded inverter. How many load inverters like the ones you have
                  built could be added to the primary, before the switching time becomes too slow? What is
                  the maximum frequency that the input can operate at if the primary inverter were loaded
                  with that many inverters?
         5.       Remove the load inverters, and replace them with an external capacitor of the same size as you
                  calculated in Step 4 above.
         6.       Measure the propagation time of the inverter, and compare with expectation.
         7.       Increase the input frequency to that calculated in Step 4. What happens to the output of the
                  inverter? Is it still reaching VDD and 0? Is it still functioning as an inverter?

         Comment on the relevance of fan out and power dissipation to modern IC devices, especially CPU
         and high speed microprocessors.


Report Content
The report must include an introduction of the laboratory experiment, the purpose for each test performed, and the
results presented in tables, with professional and clearly labeled images of measurements obtained with the
oscilloscope.

Analysis must be performed, and each statement question in bold text must be addressed and/or figures included.
Be sure to address each question with respect to the lab objectives.

Finally, a conclusion must be included in which the lab is summarized and fundamental concepts are explained in a
practical and physically significant sense.




South Dakota State University                                         EE321 Electronics II Laboratory Manual
Electrical Engineering Department                                             DarenDavoux        Summer 2008
                                                        4

				
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