Introduction to Microprocessors and Microcomputers (PowerPoint)

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					           Lecture 1: Introduction to
Microprocessors and Microcomputers

           Seungryoul Maeng
        Computer Science, KAIST

               Fall 2000


• Course Grading:
   – 강의 : 60 %
      • 중간 시험 : 25%
      • 기말 시험 : 25%
      • 기타(숙제, 퀴즈 등) : 10%
           – 강의 출석 : 특별한 사유 없이 5번 이상 결석하면 강의점수가
   – 실험 : 40%
• Course Texts:
   1. The 80386, 80486, and Pentium Processor, Walter A. Triebel,
      Prentice Hall.
   2. 실험 노트

                                                           Maeng Lect01-2

• 강의 교수
   – 맹 승렬, Room 3438,
   – home page :
   – Office Hours : Mon, Wed. 13:00 - 14:30
• TAs
   – 이재원

• Course Description
• 실험
   – 2 명이 한조를 이룸

                                                     Maeng Lect01-3
           What is a microcomputer system?

• Block diagram of a digital computer


       Input          CPU          Output

• Block diagram of a microcomputer system

   Input          Microprocessor        Output
                                                 Maeng Lect01-4
                                        NMOS Inverter

NMOS Transistor(NMOS FET)

                                  SiO2 산화막(약 0.6 micron)

      P type silicon
                                    gate oxide(약 0.05 micron)

                                    polysilicon(Low Pressure Chemical
                                    Vapor Deposition 으로 얹음)

                       AS 이온 주입
                                   Source, drain 영역 형성

      n+                n+
                                                                Maeng Lect01-5
          NMOS Inverter

          산화막 성장
n+   n+
           contact 부분 식각후
           aluminum 증착, 패턴 형성

n+   n+
                   Length unit --- l


                              Maeng Lect01-6
                         What is a microprocessor?

• Criteria
   –   number of chips
   –   data path
   –   address space
   –   CPU performance
   –   Price
• Types of microprocessor
   – Application
       • Re-programmable microprocessors
       • embedded microprocessors and micro-controllers
   – Instruction complexity
       • CISC
       • RISC
                                                          Maeng Lect01-7
                                               Classes of Computers

• What is the difference between main, mini, and micro?
    – The capacity and performance of the electronics used to implement
      their building blocks and the resulting overall system capacity and

• CPU performance
         circuit switch tim e  levels of logic   package delays clock cycles per instruction

                Tech Driven                                               Machine

                                                                                    Maeng Lect01-8
      Microprocessor Architecture의 특징

• different from the architectures of large main frames? Why?
• One or a few VLSI chips
• VLSI environments
   – density per chip
       • die size ---- yield
       • feature size --- 1.0 micron, 0.3 micron
   – I/O pad
       • chip cost
       • power consumption
       • propagation delay

                                                   Maeng Lect01-9
   The History of Intel’s Microprocessors

• Intel 4004
   – 1971, 4-bit
• Intel 8008
   – 1972, 8-bit
   – Originally designed for Datapoint Corp. as a CRT display
• Intel 8080
   – 1974, April - Altair 8800, 1975, MITS( 256 bytes of Mem, $395)
   – Apple II -- Steve Jobs and Steve Wozniak 1976, Apple 사 설립
   – Bill Gates and a fellow student : BASIC, 1975 --> Microsoft
• Intel 8086/8088
   – 1978, 16 bit: 8088, 1979, 8-bit external bus
                                                          Maeng Lect01-10
   The History of Intel’s Microprocessors

   – IBM PC ; 1981
   – 29,000 Trs
• Intel 80286
   –   1982, 16-bit architecture
   –   24-bit addressing, memory protection and virtual memory
   –   16 MB of physical MEM and 1 GB of virtual mem
   –   130,000 Trs onto a single chip
   –   IBM PC/AT in 1984, IBM PS/2 Model 50 and 60
• Intel 80386
   –   1985, 32 bits
   –   3~5 MIPS (7 MIPS on the 25 MHz chip)
   –   memory paging and enhanced I/O permission features
   –   4GB programming model
                                                            Maeng Lect01-11
   The History of Intel’s Microprocessors

• Intel 80486
   – 1989 Spring COMDEX show -> 1990 June : actual release
   – 1,200,000 Trs
   – 386+387+8K data and instruction cache, paging and MMU
• Pentium
   –   1993
   –   110 MIPS on 66 Mhz Chip
   –   16 KB on-chip cache and 64 bit data bus
   –   superscalar technology (two instructions/clock)
   –   3.1 million transistors

                                                         Maeng Lect01-12
   The History of Intel’s Microprocessors

• Pentium Pro
   – 1995, Superscalar(three-way issue)
   – 5.5 million Trs in the CPU core + 15.5 million Trs in the secondary
     cache 8K data, 8K instr cache
   – 256 KB SRAM secondary cache
   – 200 SPECint92 at 133 MHz
   – 2.9 V, 0.6 micron BICMOS
• Pentium II
   –   Pentium Pro + MMX, 1997
   –   233, 266, upto 450 MHz
   –   7.5 million Trs in CPU
   –   512KB in secondary cache

                                                           Maeng Lect01-13
   The History of Intel’s Microprocessors

• Pentium III
   –   1999
   –   Pentium Pro + MMX + Internet Streaming SIMD Instructions
   –   0.25 micron, 9.5 million Trs
   –   600 MHz, 550 MHz,...
   –   32 K(16K/16K) non-blocking level 1 cache

                                                        Maeng Lect01-14

80386-based PC/AT-Compatible System

                                   82345                        386DX+82340 chip set
 386DX                              Data

                                                   SYSTEM BUS
                     LOCAL BUS

                                  82346                                82341
387 DX                            System                             Peripheral
                                 Controller                           Combo

82385DX                           82344
 Cache                             ISA
Controller                       Controller

                                              Industry Standard Architecture(ISA) Bus
                                                                         Maeng Lect01-16
           Pentium Processor/82430 PCIset ISA

Host Bus                   Pentium Processor

                                       82434                     82433
             SRAM                                     DRAM
                                       PCMC                       LBX

                       82378 SIO               Graphics      PCI devices


                                                                   Maeng Lect01-17
                            ISA Bus Interface Signals
Pin       Name      Ty pe      Pin      Name     Ty pe
 A1    I/O CH CK*      I       B1        GND
 A2         D7       I/O       B2    RESET DRV    O
 A3         D6       I/O       B3         +5V
 A4         D5       I/O       B4       IRQ2       I
 A5         D4       I/O       B5         -5V
 A6         D3       I/O       B6       DRQ2       I
 A7         D2       I/O       B7       -12V
 A8         D1       I/O       B8    RESERVED
 A9         D0       I/O       B9       +12V
A10   I/O CH RDY       I       B10       GND
A11        AEN        O        B11    SMEMW*      O
A12        A19        O        B12    SMEMR*      O
A13        A18        O        B13      IOW*      O
A14        A17        O        B14       IOR*     O
A15        A16        O        B15     DACK3*     O
A16        A15        O        B16      DRQ3      I
A17        A14        O        B17     DACK1*     O
A18        A13        O        B18      DRQ1      I
A19        A12        O        B19   REFRESH*     O
A20        A11        O        B20     CLOCK      O
A21        A10        O        B21      IRQ7      I
A22         A9        O        B22      IRQ6      I
A23         A8        O        B23      IRQ5      I
A24         A7        O        B24      IRQ4      I
A25         A6        O        B25      IRQ3      I
A26         A5        O        B26     DACK2*     O
A27         A4        O        B27        T/C     O
A28         A3        O        B28      BALE      O
A29         A2        O        B29        +5V
A30         A1        O        B30       OSC      O      Maeng Lect01-18
                ISA Bus Interface Signals

Pin   Name    Ty pe      Pin       Name       Ty pe
C1    SBHE*     O        D1    MEM CS 16 *      I
C2     LA23     O        D2     IO CS 16*       I
C3     LA22     O        D3        IRQ10        I
C4     LA21     O        D4        IRQ11        I
C5     LA20     O        D5        IRQ12        I
C6     LA19     O        D6        IRQ13        I
C7     LA18     O        D7        IRQ14        I
C8     LA17     O        D8       DACK0*       O
C9    MEMR*     O        D9        DRQ0         I
C10   MEMW*     O        D10      DACK5*       O
C11    SD08    I/O       D11       DRQ5         I
C12    SD09    I/O       D12      DACK6*       O
C13    SD10    I/O       D13       DRQ6         I
C14    SD11    I/O       D14      DACK7*       O
C15    SD12    I/O       D15       DRQ7         I
C16    SD13    I/O       D16         +5V
C17    SD14    I/O       D17     MASTER*        I
C18    SD15    I/O       D18        GND

                                        Maeng Lect01-19
               Block Diagram of the System Board



                                                             ISA Bus
                                         data     addr                    Memory

                            DMA             MEM                           I/O

•   All signal lines are TTL compatible. Fan-out are two low power Shottkey(LS) TTLs.
•   SA0 through SA19: System Address Bus:(I/O)
     –    to address memory and I/O devices; 16MB of memory with LA17 through LA23
     –    input when CPUHLDA is high and MASTER* is low; output at all other times
     –    SA bus driven by CPU when CPUHLDA is low; SA bus driven by 8237 DMA controller when
          CPUHLDA is high
     –    latched with an internally generated ALE signal

                                                                                  Maeng Lect01-20
•   LA17 through LA23 (Latchable Address Bus); I/O
     –   the same as SA19-SA0
•   MEMR* (Memory Read, active low); I/O
     –   Input when CPUHLDA is high and MASTER* is low
     –   it is driven from the 288 bus controller when CPUHLDA is low and MASTER* is high
     –   it is driven by the 8237 DMA controller when CPUHLDA is high and MASTER* is high
     –   requires an external 10K pull-up resistor
•   MEMW*(Memory Write, active low): I/O
     –   Input/output determination: the same as MEMR*
     –   requires an external 10K pull-up resistor
•   SMEMR*(Memory Read): I/O
     –   Input/Output determination: the same as MEMR*
     –   active on memory read cycles to addresses below 1 MB.
     –   requires an external 10KW pull-up resistor
•   SMEMW*(Memory Write):I/O
     –   Input/Output determination: the same as MEMR*
     –   active on memory read cycles to addresses below 1 MB.
     –   requires an external 10K pull-up resistor
•   SBHE*(System Byte High Enable) : I/O
     –   controlled the same way as the SA bus                                  Maeng Lect01-21
•   REFRESH*(Refresh signal); I/O
•   SYSCLK(System Clock) : O
     –   this output is half the frequency of the BUSCLK input
     –   BALE, IOR*, IOW*, MEMR*, MEMW* are synchronized to SYSCLK
•   OSC(Oscillator): I-TTL
     –   the buffered in/out of the external 14.318 MHz oscillator.
•   RSTDRV(Reset Drive): O
•   BALE(Buffered Address Latch Enable): O
     –   A pulse which is generated at the beginning of any bus cycle initiated from the CPU.
•   AEN (Address Enable): O
     –   goes high anytime the inputs CPUHLDA and MASTER* are both high
     –   DMA controller has control when this signal is active
•   T/C (Terminal Count): O
     –   indicates that one of the DMA channels terminal count has been reached
•   DACK7*- DACK5*, DACK3*- DACK0* (DMA Acknowledge): O
•   DRQ7-DRQ5, DRQ3-DRQ0 (DMA Request) : I
     –   DRQ0-DRQ3 : from 8-bit I/O adapters to/from system memory
     –   DRQ5-DRQ7: from 16-bit I/O to/from system memory
     –   DRQ4 is not available externally as it is used to cascade the two DMA controllers together.
                                                                                       Maeng Lect01-22
•   IRQ15-IRQ9, IRQ7-IRQ3, IRQ1 (Interrupt Request) : I
     –   inputs for the 8259 megacells
     –   IRQ0, IRQ2, IRQ8 ; not available as external inputs
•   MASTER* (Master) : I
     –   used by an external device to disable the internal DMA controllers and get access to the system
     –   when asserted it indicates that an external bus master has control of the bus.
•   MEMCS16* (Memory Chip Select 16-bit) : I
     –   used to determine when a 16-bit to 8-bit conversion is needed for CPU addresses
     –   A 16 to 8 conversion is done anytime the System Controller requests a 16-bit memory cycle
         and MASTER* is sampled high.
•   IOCS16* (I/O Chip Select 16-bit) : I
     –   functions the same way as MEMCS16* signals
•   IOCHK* (I/O Channel Check): I
     –   used to indicate that an error has taken place on the I/O bus
•   IOCHRDY (I/O Channel Ready) : I
     –   pulled low in order to extend the read or write cycles of any bus access when required
     –   the default number of wait states for cycles initiated by the CPU;
           • four wait states for 8-bit peripherals
           • one wait state for 16-bit peripherals
           • three wait states for ROM cycles
     –   One wait state is inserted as the default for all DMA cycles                    Maeng Lect01-23
•   WS0* (Wait State 0) : I
     –   pulled low by a peripheral on the bus to terminate a CPU controlled bus cycle earlier than the
         default values

                                                                                       Maeng Lect01-24

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