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```									EXPERIMENT #3
Multi-Function Gate

Objective:
To design and build a Multi-Function Gate using the Xilinx's FPGA tools and to
document the design. Xilinx's FPGA tools will be used to design, simulate and implement
this multi-function gate to the BASYS Board FPGA.

Discussion:
The Multi-Function gate in this experiment is a double input, single output gate that can
be instructed to perform four different logic operations by placing a control value on the
inputs X and Y. The instruction to this Multi-Function Gate is provided by the operation
select bits, which thus determine how the gate will act. Figure 3.1 shows the block
diagram of such a gate. A and B form the data inputs and F the single output. X and Y are
the operation select lines.

A
Multi-Function Gate                      F
B

X         Y
Figure 3-1: Block Diagram of Multi-Function Gate

Design Specifications:
The circuit should be synthesized such that for a given X and Y, F is a certain function of
A and B. A typical multi-function gate specification may be as follows: a NOR to be
implemented when X=0 and Y=O and an XOR to be implemented when X=O and Y=l,
and so on. The multifunction gate that you are to design is as follows: The operations for
XY = 00, 01, 11, 10 are AND, OR, NAND, and NOR respectively.

3- 1
Pre-Laboratory Assignments:
1. Read this experiment carefully to become familiar with the experiment.

2. Represent the output F as a function of X, Y, A and B on a truth table.

3. Write the minimum logic expression, as a sum-of-products for the function F.

4. Draw logic diagrams for the above expressions using AND's, OR's, and Inverters.

Procedure:
1. Design and simulate this circuit using Xilinx's ISE using the schematic capture tool
and the simulation tool. Generate printouts of the schematic circuit, timing diagram
and test bench inputs. Be sure that all the sixteen input conditions have been met for
A, B, X, and Y. You will need to set the test bench end time to 4000 nano-seconds
and the simulation end time also to 4000 nano-seconds to have enough time to cycle
through all possible inputs. See Experiment #2 (pg 3) on how to set the test bench end
time and the simulation end time.

2. Now implement the design in Step 1 of this procedure and configure the FPGA so
that A is on SW0, B is on SW1, X is on SW6, and Y is on SW7. Also use LED7 for
the output F. Appendix D gives the pin details for the switches and the LEDs.
Download the FPGA configuration file to the BASYS board using the EXPORT
program as described in Experiment #1 of the laboratory. Verify that for all 16 inputs
the output F matches the truth table in Step1.

3. Repeat Step 1 but this time design and simulate the Boolean circuit using the
VERILOG language in the ISE. Generate printouts of the VERILOG file, timing
diagram and test bench inputs. Be sure that all the sixteen input conditions have been
met for A, B, X, and Y. Set the test bench end time to 4000 nano-seconds and the
simulation end time also to 4000 nano-seconds. You may need additional wires
beyond the input and output wires (eg. Wire a, b, c, d, e, etc).

4. Implement the design in Step 3 of this procedure on the BASYS board using the same
configuration given in Step 2. Verify that for all the 16 inputs the output F matches
the truth table in Step 1.

Questions:
(To be incorporated within the Conclusion section of your lab report.)

1. Can this Multi-Function Gate be operated as an Inverter? If yes, explain how.

2. Will the change in the number of inputs or outputs affect the number of operation
select lines? Explain.

3. Will the change in the number of functions alter the number of operation select lines?
Explain.

3- 2
4. Have you met all the requirements of this lab (Design Specification Plan)?

5. How should your design be tested (Test Plan)?

3- 3

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