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AN012 A Handy Method to Obtain Satisfactory Response of Buck Converter Introduction Analysis: The focus of this application note is to help users to Fig.1 shows the unity feedback system for Buck select a good set of components of the compensation converter. We first identify transfer functions for each section of the Buck converter. Traditionally, engineers of the corresponding block. first concern about the power circuit for a circuit design. After meeting the power requirement, what follows is As to the modeling of the low-frequency behavior of control loop design. The first priority of control design is power switches in square-wave power converters, the stability. And after that, the choice of components please refer to appendix [1]. The circuit of Buck can substantially effect the transient response. Here converter is shown in Fig.2 and the model of its power shows a simple method to obtain a satisfactory switches is shown in Fig.3. Please note that the circuit transient response with an acceptable steady state in Fig.3 is linear. Fig.4 shows the circuit for small signal error. analysis. + dVOUT(s) Gc(s) PWM Gp(s) dVOUT(s)=0 _ dVc(s) dD(s) Fig.1 The Unity Feedback Control Loop for Buck Converter R1 VOUT + VIN R2 Fig. 2 Buck Converter October, 2001 1 AN012 VOUT + R VIN D* IL D* Fig.3 R = DR1 + (1 − D)R 2 dVOUT(s) L rL rc R RL + S VIN * Fig. 4 Small Signal Circuit The transfer function of output with respect to duty ratio is: 1 1 1 + RL 1 rC + dVOUT (s) sc = VIN × dD(s) 1 sL + (R + rL ) + 1 1 + RL 1 rC + sc … … ..(1) (CRL rC )s + R L = VIN × L(R L C + rC C)s + [L + C(RR L + rL R L + RrC + rCrL + R L rC )]s + (R L + R + rL ) 2 where: when RL is >> rL , rC and R VIN: input voltage Equation 1 can be simplified as below: VOUT: output voltage dVOUT (s) rC Cs + 1 = VIN × R: the equivalent resistance of power switches. dD(s) L LCs 2 + [ + C(R + rL + rC )]s + 1 L: the inductor RL 1 C: the output capacitor s+ V ×r rC C rL: the DC resistance of inductor. = IN C × L 1 R + rL + rC 1 rC: the ESR of output capacitor. s2 + [ + ]s + CRL L LC RL: the loading of Buck converter. … … … … … … … … … … … … ..(2) October, 2001 2 AN012 1 According to its frequency response in Fig. 7, the where the zero ZP is at rC C network has high gain at low frequency, which helps to 1 reduce the steady state error. The attenuation of gain the ω n = at high frequency helps to weaken the noise LC disturbance. C3 R2 C2 dVout(s) R1 _ dVc(s) + Fig. 6 The Compensation Network Fig. 5 The Simulation of Typical Frequency REsponse of Buck Converter Fig. 7 The Simulation of Typical Frequency Fig. 5 represents the simulation of typical frequency Response of the Compensation Circuit response of Buck converter. Note that the effect of complex conjugate poles of LC will make the gain Its transfer function is: curve at -40dB/decade and phase curve towards -180°. dVC (s) 1+ R 2C2s And after the region around ωn, we will meet the zero, = ×β … … dVOUT (s) sR1 (C 2 + C 3 )[1 + sR 2 (C 2 //C 3 ) which is donated by the E.S.R of output capacitor. The … … … … … … … … … (4) gain curve becomes -20dB/decade and the phase is Where: towards -90°. the first pole P0 is at zero frequency (ω=0). 1 As to the PWM (Pulse Width Modulation), its transfer one zero Z1 is at R 2C 2 function is dD(s) 1 the 2nd pole P2 is at = … … … … … … … … … … ..(3) dVC (s) VM 1 1 ≈ ( when C3<<C2 ) R 2 (C 2 //C 3 ) R 2C3 where VM is the amplitude of ramp in PWM. 1 gain at low frequency: GC (s ) = About the compensation network, we choose the type sR1(C 2 + C 3 ) that is shown in Fig. 6. gain at middle frequency: October, 2001 3 AN012 R 2C 2 the origin pole is already set. Then here comes the GC (s ) = … ..(Constant) R1 (C 2 + C3 ) strategy for the location of the zero and the second 1 pole. gain at high frequency: GC (s ) = sR1C 3 For the reason of stability, the zero of compensation β is the gain of the feedback resistor divider. network must be set lower than the zero of Buck Note that due to the origin pole, the phase at low frequency is -90° and the gain curve is at -20dB/ converter. Without compensation zero, the zero of decade. When the frequency approaches to zero, the Buck converter would face three poles before it. The phase increases toward 0° with a flat gain curve. When phase of the loop transfer function falls down toward it moves toward the second pole, the frequency will be -270° and passes through -180° between the poles of towards -90° and the gain curve goes back to -20dB/ LC and the zero of Buck converter. This situation can decade again. lead to an unstable condition. To avoid that, the compensation circuit zero is advised to be lower than Control Strategy that of Buck converter. However the location of the The loop transfer function of Fig.1 is shown as below: compensation zero will affect the phase margin around T(s) = G C (s) × PWM × G P (s) the crossover frequency. To improve the phase margin 1 R 2 C 2 (s + ) of the loop transfer function and keep high gain at low R 2C2 = frequency, the compensation zero is suggested 1 sR 1 (C 2 + C 3 )R 2 (C 2 //C 3 )(s + R s (C 2 //C 3 ) 1 between ωn and 0.1 × ωn. (ωn= ). 1 LC rC (s + ) 1 rC C ×ß × × VIN × The second pole of compensation network is VM 1 R + rC + rL 1 L[s 2 + ( + )s + ] suggested far from the zero of Buck converter. In this CR L L LC way, we can obtain the –20dB/decade slope around .… … … (5) the crossover frequency. According to the sampling After meeting the power circuit requirement, we start theorem, the second pole of compensation network is to design the control loop. Therefore the LC poles and suggested to be under one fifth of switching frequency output capacitor zero are already allocated. What we can do is to distribute the location of pole and zero of 1 of Buck converter ( f Switching ) to reduce the noise at 5 compensation network to achieve the desired response demand. To obtain high gain at low frequency, high frequency. + dVOUT(s) Gc(s) PWM Gp(s) dVOUT(s)=0 _ dVc(s) dD(s) Fig. 8 The Unity Feedback Control Loop for Buck Converter October, 2001 4 AN012 Design Example response are shown in Fig. 10 and Fig. 11, respectively. Obviously, the rising time is too long and the overshoot Design example: is too large. To increase the speed of response and to VIN=8V,VOUT=5V, the operation point of output current have more phase margin, we try to extend the is 1A crossover frequency. L=27µH, rL=38.5mΩ C=1000µH, rC=52mΩ MOSFET=IR3103, RDS-ON=14 mΩ RL=5Ω VM=1.3V Design Procedure: 1. Construct the model of Buck converter and obtain the transfer function. dVOUT(s) 27µH 38.5m 14m 52m Fig. 10 The Transient Response (Ch2 is Current 5 + S Curve, 1A/div) VIN * 1000µF Fig. 9 The Model of the Given Buck Converter dVOUT (s) 1.93k (s + 19.2k ) = 8× 2 … … … … … ..(6) dD(s) s + 4.07ks + 37M From equation (6), the location of zero and the complex conjugate poles can be easily obtained. 2. Locate the zero and the second pole of compensation network. Fig. 11 The Corresponding Simulation of Since ωn= 6.08k, Frequency Response zero of Buck= 19.2k, fSwitching= 200kHz= 1.25M(rad/s) According to equation (4), we can add the extra gain Let zero of compensation network=2.04k which is provided by the compensation network at the Pole of compensation network=250k middle frequency without changing the location of zero and pole of the original loop transfer function. 3. Choose the components: Let R2=560k, then 1 According to the equation (4), R2C2= C2=875 ≈ 820p Let R2=75k then C2=6800p, and C3=56p 2.04k The transient response and the simulation of frequency October, 2001 5 AN012 1 idea to verify the steady state error by the load R2C3= … … … … … … . C3=7.14 ≈ 8p 250k regulation. From Fig.14, it shows that the steady state error of two settings is small, and the two curves are almost identical. 5.1 5.05 Vout(V) 5 C2=820p R2=560k 4.95 C3=8p C2=6800p R2=75k C3=56p 4.9 0 2 4 6 8 10 12 Iout(A) Fig.12 The Transient Response (Ch2 is current curve, 1A/div) Fig.14 The Comparison of Load Regulation of Different Components (VIN=8V, VOUT=5V) From the results of transient response and the steady state error, the second set of components can achieve a satisfactory response. Summary By taking the advantage of a high gain at low frequency with a low gain at high frequency, the best performance of the Buck Converter can be achieved. The objectives are to improve the steady Fig.13 The Corresponding Simulation of state error at low frequency and reduce noise Frequency Response disturbance at high frequency. The key points of the compensation are: Referring to Fig. 13, the crossover frequency of open 1) Locate the zero around the LC resonant loop transfer function is raised. And we could also frequency for the issue of stability. expect the bandwidth of the closed loop transfer function being increased. Indeed, in Fig 12, the set of 1 2) Locate the pole around f Switching for the noise 5 control components, which we just used, shows high speed of response and less overshoot. reduction at high frequency. 3) The combination of the above 2 procedures can Although the pole at origin (according to equation (5)) make the crossover frequency at the -20dB/ means the infinitive gain at DC (ω=0), it is still a good decade situation. Thus a satisfactory phase October, 2001 6 AN012 margin is achieved. Reference: [1] Yim-Shu Lee, Computer-Aided Analysis and Design of Switch-Mode Power Supplies., Marcel Dekker, Inc. Hong Kong,1993 October, 2001 7

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posted: | 8/23/2011 |

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